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sharc ? melody ? ultra audio processor adsst-sharc-melody-ultra summary high performance 32-bit a u di o processor super har v ard architecture computer (sharc) 4 independent buses for dual data, instr u ction, and nonintrusive, z e ro-overhead i / o fetch on a single cycle code compatible with all othe r sharc family dsps single-instruct i on-multiple-data (simd) computational architecturetwo 32-bit ieee floating-point computation units, each wit h a mult iplier, alu, shifter, and register f i le serial ports off e r i 2 s support via 8 programmable and simultaneous r e ceive or trans m it pins, which support up to 16 transmit or 16 receive cha nnels of au dio integrated peri pheralsintegrated i/o proce ssor, 1 mbit on-chip dual-p orted sram, s d ram controller, glueless multiprocessing features, and i/o ports (serial, link, external bus, spi?, and j t ag) sharc me lody ultra s u pports 32-bit fixe d-point, 32-bit floating-point, and 40-bit floating-point for m ats alu mult data register file (pey) 16 40-bit barrel shifter mult alu data register file (pex) 16 40-bit timer instruction cache 32 48-bit dag1 8 4 32 program sequencer dag2 8 4 32 32 pm address bus dm address bus 32 bus connect (px) pm data bus dm data bus 64 64 core processor spi ports (1) serial ports (4) link ports (2) dma controller 5 16 20 4 iop registers (memory mapped) control, status, and data buffers i/o processor two independent dual-ported blocks addr data data data addr addr data addr processor port i/o port block 0 block 1 dual-ported sram host port addr bus mux multiprocessor interface data bus mux 32 24 external port 6 12 8 jtag test & emulation gpio flags sdram controller ioa 18 iod 64 barrel shifter f i gur e 1 . f u nctio n al bl oc k dia g r a m in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the proper ty of th eir respectiv e co mpan ies. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2003 analog de vices, i n c. al l r i ght s r e ser v ed . rev. 0
adsst-sharc-melody-ultra table of conte n ts e y f e a t ur es g e eral d e s c r i t io h a r d a r e ar c i t e c t u r e s o t a r e ar c i t e c t u r e s h ar c m e lo d y u l t r a f a il y c o r e ar c i t e c t u r e s h ar c m e lo d y u l t r a m e o r y a d io i t e r ace f e a t ur es p i f u c t i o d e s c r i t io s b o o t m o des s e c i ic a t io s re co e de d o era t i c o di t i o s e l e c t r ical c a r ac t e r i s t ics a s o l u t e m a i u r a t i s t i i s e c i ic a t io s p o e r dis s i a t io o u t u t dr i e c u r r e ts t e st c o di t i o s e ir o e t a l c o d i t io s p i c o iura t io p i l a yo u t s u a r y o u t l i e di e s io s or der i g u ide reisi on h i s t or re i s i o i i t ial e r s i o rev. 0 | page 2 of 2 8
adsst -sharc-melody-ultra key featur es 100 mh z (10 ns ) core instruction rate single-cycle in struction execution, includin g simd operations in both computati o nal units 600 mflops pea k and 400 mf lops sustaine d p e rformance 225-ball 17 m m 17 mm mb ga package decodes indus t ry-standard fo rmats, using a 32-bit floating- point implementation deco ders: dolby digital, dolby pro logic ii dolby virt ual s p eaker techno logy, dolby he adphone dts-es exten d ed s u rro und ( i ncluding dts - es discrete and dts - es ma trix ), dts - 96/2 4 , dts neo : 6 thx ultra 2 srs labs circle surround ii mpeg2 (mc), mp3 (mpeg1 a u dio layer 3) pcm hdcd delay management bass management mpeg-2 aac waves urround virtua l louds p eaker, virt ual headphone encoders: do lby digital c o nsumer enco der single-chip dsp based implementation of digital audio algorithms sharc me lody ultra processor featur es 10 0 m i ps and extensive on-c hip memory i 2 s compatible serial ports interface to external sdr a m easy inter f aces to audio codec s 192 k hz processing supports customer specific postprocessing automatic stre am detection automatic code loading easy-to-use sof t ware architecture optimized libr ary of routines host communication using spi port supports iec 60958 for bit s t r eams 8-channel out p ut downsampling 96 k hz to 48 khz (2-channel) rev. 0 page 3 of 2 8
adsst-sharc-melody-ultra gene ral description the s h ar c m e lo d y u l tr a fa mil y o f p o w e r f u l 32-b i t a u dio p r o c es s o rs f r o m analog d e vices ena b les f l exi b le desig n s an d deli vers a h o st of fe a t ur es acr o ss hig h - e nd and h i g h f i del i ty a u dio sys t e m s to th e a v r e cei v er a nd d v d mark ets. i t in cl ude s m u l t icha n n el a u dio de co ders, en co ders, a nd p o st p r o c ess o rs for dig i t a l a u dio de sig n s usin g dsp s in h o m e t h e a ter sy stem s and au t o m o t i v e au d i o r e c e i v e r s . w i t h 32-b i t a u di o q u ali t y , th e s h a r c m e lod y u l tra a u d i o p r o c ess o r a u to d e te c t s and de c o des a u dio fo r m a t s in r e a l t i me, ena b lin g e nd us ers t o en jo y a t h e a t e r - q u ali t y a u dio exp e r i en ce i n t h e i r ho me s a n d a u to mo bi l e s . the desig n s can b e c u s t omi z e d t o m e e t t h e exac t r e q u ir emen t s o f th e a p p l ic a t ion. this a u dio d s p sys t e m ena b l e s desig n ers t o mak e val u e addi t i o n s t o p r o d uc t fe a t ur es w o rki n g o f f t h e hig h - e n d b a se fu n c ti o n a l i t y w i th wh i c h t h e y a r e p r o v i d ed . e v a l ua t i o n b o a r ds, s a m p le a p pli c a t ion s an d a l l n e ce ss a r y s o f t - w a re supp or t ( e . g . , d r ive r s ) are a v ai l a bl e. t h e e v a lu a t i o n b o ard ena b les o e ms to o f fer co m p r e hen s i v e and sin g l e -c hi p im p l e- m e n t a t io n s o f ad van c e d fe a t ur es fo r en d-us er pr o d uc ts. s h arc m e lo d y u l t r a a u dio p r o c es s o rs ena b le o e ms to p r o d uce hig h q u a l i t y , lo w co st desig n s fe a t ur in g de co d e r a l go r i t h m s an d p o st- pro c e s s o r s for dt s - e s e x te nd e d su r r ou nd ( i n c lu d i ng b o t h d t s dis c r e t e 6. 1 a nd d t s m a t r ix 6.1), d t s n e o:6, dol b y dig i - t a l, d o lb y pro l o g i c i i , d o lb y h e ad p h one, d o lby v i r t u a l s p e a k e r t e c h n o l o g y , t h x u l t r a 2 , h d c d , m p e g 1 a u d i o l a y e r 3 (als o kn o w n as mp 3), mp eg2 m u l t ic ha nne l , aa c, w a v e s u r - r o un d , s r s l a bs ? cir c le s u r r o u n d ii, a nd st er eo . i t addi tio n al l y i n c l ud es a u d i o en co d e r s f o r d d c e . the cos t o f de ve lo p m en t is r e d u ce d , ena b li n g c o mm on s o l u - t i o n s acr o ss p r o d uc t li n e s. f i eld a nd r e m o tely upg r ade a b l e p r o d uc ts wi t h pr o g ra mma b l e d s p s and a n op t i mi ze d l i b r a r y o f r o u t i n e s , a l o n g w i th th e b e s t d e v e l o p m e n t t o o l s i n th e i n d u s t r y , re d u c e t h e t i me to m a r k e t . s h ar c m e lo d y u l t r a is t h e com p r e h e n s i v e a n sw er t o t h e ne e d s o f t h e hig h -e nd , hig h qua l i t y di g i t a l a u dio ma r k e t . i t deli vers a r e a l ist i c hig h f i deli ty a u dio ex p e r i en ce a l o n g w i t h t h e max i m u m n u m b er o f fe a t u r es in t h e p r o d u c t, acr o ss p r ice p o in ts in t h e high-en d h o m e th e a t e r an d d v d ma rk ets. hardware architecture h a r d w a r e a r c h i t ect u r e in c l ud es th e in t e rfa c e bet w een t h e d s p a nd t h e h o st mi cr o c o n t r ol ler , co mman d p r o c essin g , da t a t r a n sfer in s e r i a l a nd p a r a l l el fo r m , da t a b u f f er ma na ge m e n t , a l gor i t h m c o mbi n a t i o ns , m i p s , an d me mor y re qu i r e m e n t s t h a t are prov i d e d . the m u l t icha nne l alg o r i t h m s a r e im ple m e n t e d o n a sh ar c m e lo d y u l t r a a v r e v a l u a t ion b o a r d . th e b o a r d is st anda lo ne a nd acce p t s a com p r e ss e d d i g i t a l b i t st r e a m as s e r i a l in pu t f r o m ld/ d vd /c d pla y ers o r st r e a m gen e r a to rs, de c o des t h e b i t st re am , a n d ge n e r a te s a p c m st re am i n re a l t i m e i n 2 - ch an ne l o r m u l t icha n n el m o d e . i t has a micr o c o n t r ol ler t o ha nd le co m- ma nds an d op t i o n s e le c t ion s f r o m a sma l l k e y p ad an d an lc d displ a y for st a t u s displ a y . sdram 128k u 32, boot rom 1m u 8 adc dac s/pdif transmitter s/pdif receiver irq gpio serial port multi- channel codec command kernel host micro 03373-0-002 f i g u re 2. s i mp lif ied bl ock d i ag r a m t o u n derst a nd t h e sh arc m e l o d y u l t r a f a mi ly ha r d wa r e a r ch i - t e c t ur e , on e sh ou ld exa m i n e i t s fo ur ma jo r b l o c ks: x the c o r e p r o c es s o r x dual - p o r t e d s r a m x ex t e rn al p o r t x inp u t / o u tp u t p r o c e s s o r t h e h a rdw a re a r ch ite c tu re of t h e sh a r c m e l o dy ult r a i s c o m - pl ex . i t has fo u r indep e nd en t b u s e s fo r d u a l da t a , o n e fo r in s t r u c t io n s , a nd on e fo r i/o fet c h. si n c e t h e four b u s e s a r e in- d e pen d en t , m u l t i p le tra n sa cti o n s ta k e p l ace w i th i n a sin g le cl o c k c y cl e. i t has two ex ter n a l p o r t s , d m a channel s , and eig h t s e r i al p o r t s. i t is a 0.35 n s t e chnolog y i c o p era t in g a t 3.3 v . th e sh a r c m e l o dy ult r a pro c e s s o r c a n b e i n te r f a c e d to e x te r - n a l pe ri ph e r al s w i t h r e la ti v e ea s e . t h e co mm uni c a t i o n bet w een th e s h a r c m e lod y u l tra p r oces so r a n d a h o s t m i cr oco n tr o l le r u t i l i z es t h e s p i b u s. the h o s t micr o c o n t r ol ler ca n b e t h e mas t e r a nd t h e s h arc m e lo d y u l t r a pr o c ess o r ca n ac t as a sl a ve. t h e p e r i ph erals c a n b e con t r o l l e d b y t h e h o s t micr o c o n t r ol ler usin g t h e spi b u s. t h e co mm uni c a t ion is b a s e d on comman d s and p a ra m e ters. s t a t us info r m a t io n r e ga r d in g t h e sh arc m e lo d y u l t r a d e co d i n g is p e r i o d ica l ly up d a te d and ma de a v a i lab l e to th e h o s t mi cr oco n tr o l le r . rev. 0 | page 4 of 2 8
adsst -sharc-melody-ultra te l o c dia r a o t e s h a r c m e lo d y ul t r a s e e ill u s t ra t e s t e o llo i a r c i t ec t u ral e a t ur es f i ur e c o u t at i o u i t s a l u u l t i l i e r a d s i t e r i t a sare d d a t a re i ste r i l e da t a addr es s e e ra t o r s d a g d a g p r ora se u e cer i t i s t r u ctio cace t i e r s i t e e t ca t ur e o de s o - c i d u al- o r t e d s r a m e te r a l o r t o r i te r a c i to o - c i e or y ad e - ri e r al s h o st o r t a d sdr a m i t e r ac e dm a c o t ro l l e r ea c e d ser i al o r t s t a g t e s t ac cess o r t e i l l u s e f a s ou r re e re c e t e sh a r c m e l o dy u l t r a co uic a t es i t t e o s t icr o c o tr ol ler u s i s p i t e s h ar c m e lo d y u l tra as a o-c i e o r y u er ta t is us ed o r s t o r i co a d s a r a e t e rs s e t y t e o s t t o t e s h arc m e lo d y u l t r a ad st a t us io r a t io r o t e s h arc m e lo d y u l t r a t er e is a de i e d r o t o c ol o r a s s i co- a ds a d o t a ii st a t us ior a t io o ce t e sh arc m e lo d y u l tr a r e cei es a coad r o te o st icr o i t il l r o c ess t e co a d ad io r t e o st icro a o u t t e s t a t us t es e coa d s ii t ia te ac t i o s s u c as e co di a d de co d i e co di ad de c o di i l l r e su l t i d a t a r o c e s si a d t e r o c ess e d da t a a y e deli er e d o er t e s e r i a l o r t f o r ea le i l e e co di t e mp da t a is acce t e d t r o u t e s e r i al o r t r o e r i erals li e a ad c o r sp d if r e cei er te mp da t a i s t e e co de d a d sto r e d i a o -c i co - r es s e d da t a u er t e s h arc m e lo d y u l t r a i l l r e a r e t e co r e s s e d r a es i iec o r a t s o ta t t ey ca e s e t o u t usi te s e r i al o r t o r spd if tra si t t e r u s i t e s e r i al o r t co r e s s e d r a es ca e do lo aded t o t e s h arc m e lo d y u l t r a er e t e y ca e de co d e d ad t e r e su l t i mp da ta ca e s e t o t e s e r i al o r t tra si t t e r ile co a d s a d da ta a r e tra s e r r e d e t ee t e o s t i cr oco - tr ol ler a d t e s h ar c m e lo d y u l tra o er t e s p i r e lia le co ui c a t io e e d s t e e l o i t e r r u ts ad a e e e ra l- u r o s e i ut o u tu t l i e s i u re softare architecture te a u dio r o c es s o rs r o aalo d e i ces ea le desi ers to a e al u e addi t i o s t o r o d uc t e a t ur es o ri o t e i - e d a s e u c t i o a l i t y t e sh a r c m e l o dy ult r a s o t a re a s t e o llo i a r t s e ecu t i e e r e l al o ri t a s li r a r y o d u le te ee c u t i e e r e l as t e ol l o i u c t i o s p o e r - u a rd a re i it i a l i a t i o se ri a l o rt a a e e t au t o a t i c s t r e a d e t e c t a u t o a tic co de lo ad c o a d ro c e s s i i te r r ut a d l i da t a u e r a a e e t c a l l i li r a r y o d u le st a t u s re o r t te ee c u t i e e r e l is ee c u t e d as s o o as o o t i t a e s l ac e te a r d a r e r e s o ur ces a r e ii t iali e d i t e e i i t e c o a d u e r ad e e r a l - u r o s e ro r a al e l a i s are i i t i a l i e d a r i ou s d a t a u e r s a d e or y a r i al e s are ii t ia li e d i ter r u ts a r e r o r a e d ad eale d t e de i - i t e si a t ur es ar e r i t t e c o a d u er t o io r t e o s t t a t t e sh ar c m e lo d y u l t r a is r e ad y t o r e cei e t e co - a ds o c e coa d s a r e issue d y t e o st icr o c o t r ol ler t ey a r e e ecu t ed a d a r o ria t e a c ti o s t a e l a c e decod i is a d le d y issui a r o r i a t e co ads r o t e o st icr o c o t r ol ler te e r e l co uic a t es i t t e l i r a r y o d u le o r a a r t ic u- la r a l o r i t i a de i e d a y te det a i l s a r e o u d i t e s e c i ic i le e t a t i o do c u e t s a s t e e r el is o d u la r i t is e a sy t o c u s t o i e t o di er e t a r d a r e la t o r s m o s t o t e ti e use r s e e d t o c a e t e i i t i a lia ti o cod e t o s u i t t e a r t ic u l a r co dec c os e decoding library executive kernel input stream output stream fi g u r e 3 . s o f t w a r e the s h ar c m e lo d y u l tr a in c l udes a 100 mh z co r e , d u a l - po r t ed o n - c hi p s r a m , a n i n t e g r a t e d i/ o p r oces so r wi th m u l t i - p r o c essin g sup p o r t, a n d m u l t i p l e in ter n a l b u s e s t o e l imin a t e i/o bot t lene c k s. the s h arc m e lo d y u l tra o f f e rs a s i n g le- in s t r u c t i o n - m u lt ip l e - d a t a ( s i m d ) a r c h it e c tu re , u s i n g t w o co m p u t a t io n a l uni t s. f a b r ic a t e d in a st a t e o f t h e a r t, hig h sp e e d , lo w p o w e r cm os p r o c es s, t h e s h ar c m e lo d y u l t r a has a 10 n s in st r u c t io n c y cle t i m e . w i t h i t s s i md co m p u t a t io nal ha r d wa r e r u nnin g a t 100 m h z, th e s h arc m e l o d y u l tra can p e r f o r m 600 mil l io n ma th o p er a - t i ons p e r s e c o n d . s h ow s p e r f or m a nc e b e nch m ar k s f o r th e s h a r c m e lod y u l tra . t a bl e 1 rev. 0 | page 5 of 2 8
adsst-sharc-melody-ultra the s h ar c m e lo d y u l t r a co n t in ues t h e s h a r c ? s i n d u s t r y - le adin g st anda rds o f in t e g r a t ion fo r ds p s , com b in in g a hig h p e r f o r ma n c e 32 -b i t ds p co r e wi th in teg r a t e d , on-c hi p sys t em fe a t ur es. th es e fe a t ur es i n cl ude a 1 mb i t d u al -p o r t e d s r am me mor y , a ho s t pro c e s s o r i n te r f a c e, an i / o pro c e s s o r t h a t s u p- po r t s 1 4 d m a c h a n n e l s , f o u r se ri al po r t s , t w o l i nk po r t s , a n s d ram con t r o l l er , a n s p i in t e r f ace , a n ext e r n al p a ral l e l b u s, and g l u e l e ss m u l t i p ro c e ss i n g . f i gur e 2 i l l u s t ra t e s th e f o l l o w ing a r c h i t ec t u ral f e a t ur es: x t w o p r o c es s i n g e l emen t s , e a ch made u p o f a n al u , m u l t i - plier , shif t e r , a nd d a t a r e g i ster f i le x da t a addr es s g e n e ra t o r s (d a g 1 , d a g2) x p r ogra m seq u en cer wi t h in s t r u ctio n cache x pm a nd d m b u s e s ca p a b l e o f s u p p o r tin g f o ur 32-b i t da ta tra n sfers betwe e n m e m o r y a n d th e co r e e v er y co r e p r o c es - so r c y c l e x int e r v a l t i m e r x on-c hi p s r am (1 mb i t ) x sdr a m c o n t rol l e r for g l u e l e ss i n te r f a c e to sd r a m s x e x t e r n al p o r t tha t s u p p o r ts x i n te r f a c i n g to of f - ch i p me mor y p e r i phe r a l s x gl u e l e ss m u l t ipro c e ss ing for s i x s h a r c m e l o dy ul t r a pro c e s s o r s x h o s t p o r t r e ad/wr i t e o f i o p r e g i s t ers x dm a c o n t ro l l e r x fo u r s e r i a l p o r t s x tw o l i n k p o r t s x s p i co m p a t ib le in t e r f ace x jt a g t e s t ac cess p o r t x 1 2 g e ne r a l - pu r p o s e i / o pi n s f i gur e 4 s h o w s a typ i cal sin g le -p r o ces s o r sys t e m . a m u l t i p r o c - es sin g sys t e m a p p e a r s i n . f i gur e 7 sharc melody ultra family cor e architecture the s h ar c m e lo d y u l t r a in cl udes t h e fol l o w i n g a r chi t e c t u ral f e a t ur es o f th e ads p -2116x famil y co r e : simd c o mp ut ational engin e t h e sh a r c m e l o dy ult r a c o n t ai ns t w o c o m p ut a t i o n a l pro c e s s - in g e l em en ts tha t o p er a t e as a sin g le i n s t r u c t io n m u l t i p le d a t a (s imd) en g i n e . the p r o c es sin g e l emen t s a r e r e fer r e d t o as p e x a nd pe y , and e a ch co n t a i n s a n al u , m u l t i p lier , shif ter , an d r e g - ister f i le. pex is a l wa y s ac t i ve, and pe y ma y b e ena b le d b y s e t t in g t h e p e y e n m o de b i t i n t h e mo d e 1 r e g i s t er . w h e n t h is m o d e is enab le d , t h e s a m e i n st r u c t io n is exe c u t e d i n b o t h p r o c - e s s i n g e l em en t s , b u t ea ch p r oce s s i n g e l em en t o p e r a t e s o n dif f er en t da t a . this a r chi t e c t u r e is ef f i cien t a t exe c u t in g ma t h - in t e n s i v e d s p a l go r i t h m s . en t e r i n g s i md m o de als o has an ef f e c t o n t h e wa y da t a is tra n s- f e rr ed be t w ee n m e m o r y a n d t h e p r oce s s i n g e l e m en t s . w h en in s i md m o de , t w ice t h e d a t a b a nd w i d t h is r e q u ire d t o sust ain co m p u t a t i o nal o p e r a t i o n in th e p r oce s s i n g e l em en t s . b e ca use o f t h is r e q u ir emen t, en t e r i n g s i m d mo de als o doub les t h e b a n d - w i d t h bet w een m e m o r y a n d t h e p r oce s s i n g e l e m en t s . w h en usin g t h e d a gs t o t r a n sfer da t a in s i md mo de , tw o da t a val u es a r e tra n sfer r e d wi t h e a ch access o f m e m o r y o r th e r e g i st er f i le . independent, paralle l computation units w i t h in e a ch p r o c essin g e l e m en t is a s e t o f com p u t a t iona l uni t s . the co m p u t a t iona l uni t s con s ist o f a n a r i t h m et i c /log ic uni t (al u ), m u l t i p li er , a n d shif t e r . th es e u n i t s p e r f o r m sin g le-c ycle in s t r u c t io n s . the t h r e e uni t s wi t h in e a ch p r o c essin g e l e m e n t a r e a r ra n g ed in p a ralle l , maximizin g co m p u t a t io na l thr o ugh p u t . sin g le m u l t if u n c t io n inst r u c t io n s exe c u t e p a ra l l e l al u and m u l t i p lier op era t io n s . i n s i m d m o de , t h e p a ral l e l al u an d m u l t i p lier op era t io n s o c c u r in b o t h p r o c es sin g elem e n ts. th es e co m p u t a t io n uni t s s u p p o r t ieee 32-b i t sin g le-p r e cisio n f l o a t- in g-p o in t, 40-b i t ex tende d p r e c isio n f l o a t i n g -p oin t , and 32-b i t f i xe d- p o i n t da t a fo r m a t s. table 1. be nch m arks (at 100 mhz) benchmark algorithm speed (at 100 mhz) 1024 point comple fft ( ad i 4 with eversal) 1 171 s f filter (per ta p) 1 5 n s filter (per biuad) 1 4 0 n s matri multipl (pipelined) 3 3 3 1 30 ns 4 4 4 1 37 ns divide ( ) 60 ns nverse suare oot 40 ns dma transfers 800 mbtess 1 assum e s t w o fi lt er s i n m u lt i c h a n n e l s md m o d e ev. 0 page 6 of 2 8
adsst -sharc-melody-ultra dma deice optional data clout dmar dmag addr data host processor interface optional cloc clin xtal ir- clcfg eboot lboot flag timexp cldbl reset tag sbts adsst sharc melod ultra bms lin deices max optional lxcl lxac lxdat scl db da fs serial deice optional cs boot eprom optional addr memor and peripherals optional oe data cs rd ras ac br rpba id- pa hbg hbr sde ms r data data addr cs ac e addr data co ntro l addre s s brst sdram optional scl db da fs scl db da fs scl db da fs spicl miso mosi spids spi compatible deice host or slae optional data cas ras dm e addr cs a ce cl dm cas red sdce sda sdcl rstout serial deice optional serial deice optional serial deice optional 03373-0-001 f i g u re 4. sy s t e m b l ock d i ag r a m i gur e 4 dat a r e gister file a g e neral-p u r p os e da ta r e g i s t er f i le is co n t a i n e d in e a c h p r o c es sin g e l e m en t. the r e g i s t er f i les t r a n sfer da t a b e twe e n t h e co m p u t a t ion un i t s and t h e da t a b u s e s, a nd sto r e in ter m e d i a te r e s u l t s. th es e 1 0 -p o r t, 32-r e g i s t er (16 p r ima r y , 16 s e co nda r y) r e g i s t er f i les, co m b i n e d wi t h t h e s h arc m e lo d y u l t r a ? s e n h a nc e d h a r v ard arch i t e c t u re , e n abl e u n c o nst r ai ne d d a t a f l ow b e tw e e n co m p ut a t ion uni t s an d in t e r n a l m e m o r y . th e r e g i st ers in pe x a r e r e fer r e d t o as r0 ?r1 5 , a n d in pe y as s0?s15. single - c y c le f e t c h of instruc t ion a n d f o ur o p er a n ds the s h ar c m e lo d y u l t r a fe a t ur es a n enhan c e d h a r v a r d a r chi - te c t u r e i n w h i c h t h e d a t a me mor y (d m) b u s tra n sfers da ta and th e p r og ra m m e m o r y (pm) b u s tra n sfers bo th in s t r u c t io n s an d da ta (se e f ) . w i th t h e s h a r c m e lo d y u l tra ? s se pa ra t e p r o g r a m a nd da t a m e m o r y b u s e s a nd o n -ch i p i n st r u c t io n cache, t h e p r o c e s s o r can sim u l t an e o us ly fet c h fo ur o p era n ds (t w o o v er e a ch da t a b u s) a nd a n in st r u c t io n (f r o m t h e cach e), a l l wi t h i n a sin g le c y c l e . instru ction ca che the s h ar c m e lo d y u l t r a i n cl udes a n o n -chi p in s t r u c t io n cach e t h a t ena b l e s 3-b u s o p er a t i o n fo r fet c hin g a n ins t r u c t io n a nd fo ur da t a v a l u es. th e cach e is s e le c t i v e?on l y t h e ins t r u c - tio n s w h os e fet c h e s co nf lic t wi th pm b u s da ta acces s es a r e ca ch ed . t h i s ca ch e e n a b l e s full s p eed e x ecu t i o n o f co r e , l o o p ed o p er a t io ns such as dig i t a l f i l t er m u l t i p ly -a cc um u l a t es and f f t b u t t er f l y p r o c es sin g . dat a a d dress gener a tors wi th hardw a r e circul ar b u ff e r s the s h ar c m e lo d y u l t r a p r o c es s o r ? s tw o da t a addr es s g e nera - to rs (d a g s) a r e us e d fo r in d i r e c t addr essin g and im ple m en t i n g c i rc u l ar d a t a bu f f e r s i n h a rdw a re. c i rc u l ar bu f f e r s e n abl e e f f i - cien t p r o g r a mm in g o f del a y li n e s a nd o t h e r d a t a st r u c t ur es r e q u ir e d in dig i tal sig n al p r o c essin g , an d a r e comm onl y us e d in dig i t a l f i l t ers and f o ur ier t r a n sf o r m s . th e tw o d a gs o f t h e s h ar c m e lo d y u l t r a con t a i n suf f i cien t r e g i s t e r s t o ena b le t h e cr ea tio n o f u p to 32 cir c u l a r b u f f ers (16 p r ima r y r e g i s t er s e ts, 16 s e co nd a r y ) . the d a gs a u toma t i c a l l y ha nd le addr ess p o in te r rev. 0 | page 7 of 2 8
adsst-sharc-melody-ultra r a arou d re d u c e oe r e a d i c r e a s e e r or a c e a d s i - li y i le e t a t i o c i r c u l a r u ers ca st a r t a d e d a t a y e or y l o c a t i o fleile istructio set te - i t i st r u c t io o r d acc o o d a t e s a a r i ety o a ra l l e l o era t io s o r co c ise r ora i f o r ea l e t e s h ar c m e lo d y u l t r a ca co d i t io a l l y ee c u t e a u l t i ly a add ad a s u t ra ct i o t r oce s s i e l e e t s il e r a c i all i t i a si le i st r u c t io a a fff bl fff bl fff bl ffff fff bl fff bl ffff ffff ffff a b ffff ffff fff bl ban ms ban ms ban ms ms iop registers long ord addressing short ord addressing normal ord addressing address ban ff ffff sdram ff ffff non-sdram ff ffff sdram ff ffff non-sdram bff ffff sdram ff ffff non-sdram c fff ffff sdram cff ffff non-sdram note ban sies are fixed ffff address resered c ffff f ffff external memor space iop registers of adsst-sharc-melod-ultra ith id iop registers of adsst-sharc-melod-ultra ith id iop registers of adsst-sharc-melod-ultra ith id iop registers of adsst-sharc-melod-ultra ith id iop registers of adsst-sharc-melod-ultra ith id iop registers of adsst-sharc-melod-ultra ith id multiprocessor memor space internal memor space f i ure meo r y ma b l oc d i a r a re pae o
adsst -sharc-melody-ultra sharc melody ultra memory and i/o interface features the s h arc m e lo d y u l t r a add s t h e fol l o w in g a r chi t e c t u ra l fe a - t u r e s t o th e ads p -2116x fa mil y co r e : dual-port e d on-chip me m o ry t h e sh a r c m e l o dy ult r a c o n t ai ns 1 m b it of on - c h i p sr a m , o r ga nize d as two b l o c ks o f 0.5 mb i t s. e a ch b l o c k can b e co nf igur e d fo r dif f er en t com b i n a t io n s o f co d e a nd da t a sto r a g e. e a ch me mor y bl o c k i s d u a l - p or te d for s i ng l e - c y c l e , indep e n d en t ac ces s es b y t h e cor e p r o c es s o r a nd i/o p r o c e s s o r . t h e du a l - p or te d me mor y i n c o mb i n a t i o n w i t h t h re e s e p a r a t e o n -c hi p b u s e s e n a b les tw o da ta tra n sfers f r o m th e co r e and on e f r o m th e i/o p r o c es s o r , wi thin a sin g le c y c l e . on the s h ar c m e lo d y u l tr a , th e m e m o r y can be co nf igur e d as a maxim u m o f 32 k w o r ds o f 32-b i t da ta , 64 k w o r ds o f 16-b i t da ta , 21 k w o r ds o f 48-b i t in s t r u c t io n s (o r 40-b i t da ta), o r com b ina t io n s o f dif f er en t w o r d s i zes u p t o 1 mb i t . a l l o f t h e m e m o r y ca n b e acces s e d as 16-b i t, 32-b i t, 48-b i t, o r 64-b i t w o r d s. a 16-b i t f l o a t i ng - p oi n t s t or age f o r m a t i s supp or te d t h a t e f f e c t ively d o ubl e s t h e a m ou n t of d a t a t h at m a y b e store d on - c h i p . c o n v ersio n b e t w e e n t h e 32 -b i t f l o a t i n g -p o i n t and 16- b i t f l o a t i ng - p oi n t f o r m a t s i s d o ne i n a s i ng l e i n st r u c t i o n . w h i l e e a ch me mor y bl o c k c a n s t ore c o mb i n a t i o ns of c o d e a n d d a t a , acces s is m o s t e f f i cien t w h e n o n e b l o c k st o r es da t a usin g t h e d m b u s fo r tra n sfers, a n d t h e o t h e r b l o c k s t o r es in s t r u c t io n s a nd da ta usin g t h e pm b u s fo r tra n sfers. u s in g t h e d m b u s an d pm b u s, wi th on e dedica t e d t o eac h m e m o r y b l o c k, as s u r e s sin g le-c yc le exe c u t io n wi t h tw o da ta tran sfers. i n this cas e , t h e in st r u c t io n m u st b e a v ai lab l e in t h e cach e . off-chip me m o ry and perip h er als int e rf ace the s h ar c m e lo d y u l t r a ? s exter n al p o r t p r o v ides t h e p r o c es - s o r ? s in ter f ace to o f f-chi p m e mo r y a n d p e r i ph e r a l s. th e 62.7 m w o r d o f f-c h i p addr es s s p ace (254 m w o r d if al l s d ram) is in cl ud e d i n t h e s h arc m e lo d y u l t r a p r o c e s s o r ? s unif ie d addr ess sp ac e. t h e s e p a r a te on- c hi p b u s e s?fo r pm addr ess e s, pm d a t a , d m addr ess e s, d m d a t a , i/ o ad dr ess e s, a nd i/o d a t a ? a re m u lt ipl e xe d a t t h e e x te r n a l p o r t to c r e a te an e x te r n a l sys t em b u s wi th a sin g le 24-b i t addr es s b u s a n d a sin g le 32-b i t da ta b u s. e v er y acces s t o ext e r n al m e m o r y is bas e d on a n ad- dr es s tha t fet c h e s a 32-b i t w o rd . w h en fet c hin g a n ins t r u c t io n f r om e x te r n a l me mor y , t w o 3 2 - b i t d a t a l o c a t i o n s are b e i n g a c - ces s ed f o r p a ck e d in str u c t io n s . u n us ed link p o r t lin e s can als o be us e d as addi t i o n al da t a lin e s d a t a [0]?d a t a [15], ena b lin g sin g le-c ycle exe c u t io n o f in st r u c t io n s f r o m ext e r n a l m e m o r y a t u p t o 100 mh z. s h o w s th e alig nm en t of va r i o u s ac- ces s es t o ext e r n al m e m o r y . f i gur e 6 f i gure 6. e x te rn al d a t a a l ignm ent o p tions 47 40 39 32 31 24 23 16 15 8 7 0 extra data lines data[15 ? 0] are only accessible if link ports are disabled. enable these additional data lines by selecting ipack[1:0] = 01 in syscon l1data[7:0] data 15 ? 8 l0data[7:0] data7 ? 0 prom boot 8-bit packed dma data 8-bit packed instruction execution 16-bit packed dma data 16-bit packed instruction execution float or fixed, d31 ?d0, 32-bit packed 32-bit packed instruction data 47 ? 16 data 15 ? 0 48-bit instruction fetch (no packing) t h e e x te r n a l p o r t supp or t s a s y n ch ronou s , s y nc h r onou s , an d s y nc h r onou s bu r s t a c c e ss . s y nc h r onou s bu r s t sr a m c a n b e in te r f ac e d g l u e l e ssly . t h e s h a r c m e l o dy ul t r a c a n a l s o in te r - f a c e g l u e l e ssly to s d r a m . a d d r e s s i ng of an e x te r n a l me mor y de vice is fac i li t a te d b y o n -ch i p de co d i n g o f hig h -o r d er ad dr ess lin e s t o g e n e r a te m e m o r y ba n k s e le c t sig n als. th e s h arc m e l- o d y u l t r a p r o v i d es p r og ra mma b l e me m o r y wa i t s t a t es and e x te r n a l me mor y a c k n ow l e dg e c o n t rol s to e n ab l e i n te r f a c i n g to m e m o r y a nd p e r i ph er a l s w i t h v a r i a b le acce ss, hold , a nd dis a b l e ti m e r e q u i r em en t s . sdram int e rface the s d r a m in t e r f ace ena b les t h e sh arc m e l o d y u l t r a t o t r ans f e r d a t a to an d f r om s y nch r onou s dr a m ( s dr a m ) a t t h e co r e c l oc k f r eq ue n c y o r o n e- h a lf th e co r e c l oc k f r eq ue n c y . th e s y nc h r onou s a p pro a ch , c o upl e d w i t h t h e c o re cl o c k f r e q u e nc y , s u p p o r t s d a ta tra n sf e r a t a hi gh th r o ugh p u t ?u p t o 400 mb yt es/s f o r 32-b i t tra n sf ers a nd 600 mb ytes/s f o r 48-b i t t r a n sfers. th e sd r a m in t e r f ac e p r o v ides a g l u e les s in t e r f ace wi t h s t anda r d s d rams (16 mb i t , 64 mb i t , 128 mb i t , an d 256 mb i t ) and in c l udes o p t i o n s t o s u p p o r t addi tio n al b u f f ers b e t w e e n t h e sh a r c m e l o dy ul t r a an d sdr a m . t h e sdr a m in t e r f ace is ext r eme l y f l exi b le and p r o v ides c a p a b i li ty fo r co n- n e c t i n g s d r a m s to an y on e of t h e s h arc m e lo d y ul t r a p r o c es s o r ? s f o ur ext e r n al m e m o r y ba nks, wi th u p t o al l f o ur ba nks ma p p e d to s d r a m. s y s t em s wi th s e veral s d r a m de - vices co n n e c t e d in p a ra l l e l m a y r e q u ir e b u f f er in g t o m e e t o v eral l sys t em t i min g r e q u ir e m e n ts. th e s h arc m e lo d y u l t r a su p p o r ts p i p e l i nin g o f t h e address an d con t r o l sig n a l s to ena b le s u c h bu f f e r i n g b e t w e e n it s e l f a n d m u lt ip l e sd r a m d e v i c e s . rev. 0 | page 9 of 2 8
adsst-sharc-melody-ultra tar et bo ar d tag e ulato r c o e ctor aalo deices ds p t o ols r o d uc t li e o t a g e u l a t o r s us es t e ieee t a g t e s t ac cess o r t o t e s h ar c m e lo d y u l tra r oce s so r t o o i t o r a d co t r o l t e ta r e t oa r d r oces- so r d u r i e u l a t io aalo deices ds p t o ols r o d uct li e o t a g e u l a t or s ro i d e s e u l a t i o at u l l ro c e s s o r s e e d ea li i s e c t i o ad o di i ca t i o o e o r y r e i sters a d r o c es s o r s t acs t e r o c es s o r s t a g i t e r ace e s u r e s t a t t e e ula t o r i ll o t a e ct ta r e t sys t e loa d i o r ti i f o r co let e io r a t io o a a l o d e i ces d s p t o ols r o d uc t l i e o t a g e u l a t or o e r at i o s e e t e a r or i a t e em u l at o r h a rdw a re u s e r ' s g u i d e o r det a i l e d info r m a t ion o n t h e i n t e r - facin g o f analog de vices j t a g em u l a t o r s wi t h analog devices ds p r o d uc ts wi th j t a g em u l a t io n o r t s l eas e r e f e r t o th e en g i n e er -t o-eng i n e er n o t e ee - an a l o g d e v i c e s j t a g e m u l a - tio n t e c h n i ca l r e fer e nc e b o t h of t h es e do c u m e n t s c a n e fo u nd on t h e a n a l o g d e v i c e s we s ite a t h t t w w w a na l o gco m ds te chdo c s h t m l dma controll er the s h ar c m e lo d y u l t r a r o c es s o r s o n -chi d m a co n t r o l l e r ena les er o -o v e rh e a d da ta tran sfers wi t h o u t r o c es s o r in t e r - ven t ion t h e dma co n t r o l l er o er a t es inde e nden t ly an d in visi l y t o t h e r o c es s o r co r e ena lin g d m a o era t io ns t o o c c u r w h i l e t h e co r e is sim u l t ane o us l y ee c u t in g i t s r og ra m in st r u c t io n s d m a t r a n sfers can o c c u r e tw e e n t h e s h arc m e l o dy ult r a ro c e s s o r s i n te r n a l me mor y an d e te r n a l me m- o r y et e r n al e r i h erals o r a hos t r o c es s o r d m a t r a n sfers can al so oc cu r e t w ee n th e s h a r c m e l o d y u l tr a r oc e s so r s i n t e r- nal m e m o r y and i t s s e r i al o r t s link o r t s o r th e s p i s er ial e ri h e r al i n t e rf a c e c o m a t i l e o r t e t e rn al u s a c k i n g a n d un a c k in g o f - - - o r - i t w o r d s in in ter n al m e m o r y is e r f o r m e d d u r i n g d m a tra n s f ers f r o m ei th er - - o r - i t wi de et e r n a l m e m o r y o ur t e en channe ls o f d m a a r e a v a i l - al e on t h e sh a r c m e l o dy ult r a t w o are sh are d e t w e e n t h e s p i in t e r f ace and t h e lin k o r t s eig h t v i a t h e s e r i al o r t s a nd fo ur via t h e r o c es s o r s et e r n al o r t fo r ei t h er h o s t r o c e s s o r o t h e r s h ar c m e lo d y u l tra s m e m o r y o r io tra n sfers p r o- gra m s ca n e do w n loa d ed t o th e s h a r c m e lod y u l tra usi n g d m a tra n sfers a s y n c h r o n o us o f f-c h i e r i herals ca n con t r o l t w o dm a c h a n ne l s u s i n g dm a re u e s t g r a n t l i ne s dm a r dm a g o t h e r d m a f e a t ur es in c l u d e in t e r r u t g e nera tio n u on c o m l e t i on of dm a t r ans f e r s and dm a ch ai n i n g for a u t o ma ti c link e d d m a tra n sf e r s multiro cessing the s h arc m e l o dy ul t r a o f fers o wer f u l fe a t u r es t a i l o r e d to m u l t i r o ces s in g ds p sys t e m s th e et e r n al o r t a nd lin k o r t s r ov ide i n te g r a t e d g l u e l e ss m u l t i ro c e ss ing su or t the et e r n a l o r t su o r ts a unif ie d addr ess s ac e s e e tha t ena les direc t in t e r r o ces s o r acces s es o f eac h s h ar c m e l o dy ult r a ro c e s s o r s i n te r n a l me mor y - m a e d i o r o c es s o r r e g i s t ers a l l o t h e r i n t e r n al m e m o r y ca n e i n dir e c t ly a c ce s s e d via d m a tra n sf e r s i n i t ia t e d th r o ugh th e r ogra m m i n g o f t h e i o p d m a a r a m e ter and co n t r o l r e g i sters dist r i u te d u s a r i t r a t ion l o g i c is in cl ude d o n -ch i fo r sim le g l ue less co nne c t io n o f s y stem s co n t a i n i n g u to si s h arc m e lo d y u l t r a r o c ess o rs a nd a h o s t r o c es s o r m a s t er r o c es s o r ch ange ove r i n c u r s on ly one c y cl e of ove r he a d bu s ar it r at i o n i s s e le c t a le as ei t h er f i e d o r r o ta tin g r io r i ty b u s lo c k ena les indivisi l e r e ad-mo d if y- wr i t e s e u ences fo r s e ma h o r es a v e c t o r in ter r u t is r o v ide d fo r in t e r r o cess o r c o mman d s t h e ma i m u m t h r o ug h u t fo r in ter r o cess o r d a t a t r a n sfers is m yt ess o v er th e et e r n al o r t t w o lin k o r t s r o v ide a s e con d m e t h o d o f m u l t i r o ces s in g co mm unic a t io n s e a c h lin k o r t ca n su o r t co mm u n ic a t ion s t o an o t her s h ar c m e lo d y u l t r a t h e s h a r c m e lo d y ul t r a r u nnin g a t mh h a s a maim u m t h r o ug h u t fo r in t e r r o cess o r co m m unic a t ion s o v er th e links o f m yt ess th e link o r t s and c l us t e r m u l t i r o ces s in g ca n e us e d con c ur r e n t l y o r inde e n d en tl y i gur e link ports the s h ar c m e lo d y u l t r a fe a t ur es tw o - i t link o r t s t h a t r o v i d e a d d i ti o n al i o ca a i li ti e s w i t h th e ca a i li t y o f r u n - nin g a t mh eac h lin k o r t ca n su o r t m yt ess l i n k o r t io is es e cial l y us ef u l f o r o in t-t o - o i n t in t e r r o ces s o r co mm uni c a t io n in m u lt i r o ce ssin g sy st e m s t h e lin k o r t s can o er a t e i n de e nden t ly an d si m u l t an e o usly w i t h a ma i m u m da ta thr o ug h u t o f m yt ess l i nk o r t da t a is a c k ed in t o - o r - i t w o r d s a nd can e dir e c t l y r e ad y th e co r e r o c es - s o r or dm a - t r ans f e r re d to on - c h i me mor y e a ch l i n k o r t h a s i t s o w n do u le- uf fer e d in u t and o u t u t r e g i sters cloc k a c k n o w le d g e h a n d s haki n g co n t r o ls li nk o r t tra n sf er s t r a n sfers a r e r og ra mma l e as ei t h er t r a n smi t o r r e cei v e serial ports the s h ar c m e lo d y u l t r a fe a t ur es fo ur syn c hr o n o u s s e r i al o r t s t h a t r o v i d e a n i n e e n s iv e in ter f ace t o a wide va r i ety o f dig i t a l an d mie d-sig n a l e r i h er a l d e vices e a ch s e r i a l o r t is made u o f tw o d a t a li n e s a clo c k a nd f r am e sy n c t h e d a t a lin e s ca n e r og ra mm e d t o e i t h er tra n smi t o r r e cei v e the s e r i al o r t s o era t e a t u t o half t h e clo c k r a t e o f t h e co r e r o v idin g e a ch wi t h a maim u m da t a ra t e o f m s t h e s e r i al da t a i n s a r e r og ra mma l e as ei t h er a t r a n smi t t e r o r r e ce i v e r r o v i d in g gr ea t e r f l e i ili t y f o r se ri al co m m un ica t i o n s s e r i a l o r t da t a ca n e a u toma t i ca l l y t r a n sfer r e d to an d f r o m on - c h i me mor y v i a a d e d i c a te d dm a e a ch o f t h e s e r i a l o r t s f e a t ur es a t i m e di visio n m u l t i le t d m m u l t ic ha nn e l m o de t w o se ri al o r t s a r e t d m tra n sm i t t e r s a n d t w o se ri al o r t s a r e td m r e cei v ers s por t r x a ir e d wi t h s p or t t x s p or t r x a i r ed w i th s p o r t t x e a c h o f th e se ri al o r t s al so su or ts t h e i s r o t o c ol a n i n d u st r y -st a nda r d in ter f ace co m m o n ly us e d y a u dio co de c s ad cs and d a cs wi t h tw o d a t a i ns e n a l i ng fou r i s ch an nel s u s i ng t w o i s s t er eo de vices e r s e r i al o r t u t o a maim u m o f i s cha nnels the s e r i al o r t s ena le li t t le-e ndian o r i g-e ndia n tra n smis sio n f o r m a t s a nd w o r d len g th s s e le c t a le f r o m thr e e i ts t o i ts o r i s m o de da ta-w o r d len g t h s a r e s e le c t a le e tw e e n eig h t rev page of
adsst -sharc-melody-ultra pas e d -loc e d loo a d c r ys tal do ul e e a le i t s a d i t s s e r i a l o r t s o e r s e l e c t a l e s y c r o i a t i o a d tra s i t o d e s a s e ll a s o ti o al - la o r a - la c o a di s e r i a l o r t clo c s a d r a e s y c s ca e i t e r a l ly o r et e r - a l l y e e r a te d te s h ar c m e lo d y u l tr a us es a o -c i as e-lo c e d lo o p l l to e e r a te t e i te r a l c l o c or t e c o re t e clcfg i s a r e us e d t o s e lec t ra tios o a d i a d d i ti o t o t e pl l ra ti os t e cld bl i ca e u s e d o r o r e c l oc ra tio o ti o s t e c l i n ra t e set y t e cld bl i de ter i es t e r a te o t e pll i u t clo c a d t e ra t e a t ic t e sy c r o o u s et e r al o r t o era t es i t t e co i a t io o clcf g a d cld bl ra tios o a d et ee t e co re a d cl i n a r e s u o r t e d s ee f i ur e serial peri e r al co a ti le ite r ac e se ri al p e ri e r al i t e r a c e s p i i s a i d u s t r y - s ta d a r d s y - c r o o us s e r i al li ea li t e s h arc m e lo d y u l tra s p i c o at i l e o r t t o c o u i c at e i t o t e r s p i c o at i l e de ices s p i is a - i r e i t e r ace co s ist i o t o da t a i s o e de ice s e le c t i a d o e clo c i i t is a u l l -d u le sy c r o- o us s e r i a l i ter ace su o r t i o t a ster a d sl a e o des te s p i o r t ca o era t e i a u l t ias t e r e ir o e t y i - t e r aci i t u t o o ur o t e r s p i co a t i le de ices ac ti as ei t er a as t er o r s l a e de ic e te s h ar c m e lo d y u l t r a s p i c o a t il e e r i er a l i l e e t a t i o a l s o e a t u r es r o r a - a l e a ud ra t e a d clo c as e o la r i t i es t e s h ar c m e lo d y u l tr a s p i co a t i le o r t us es o e-dra i dr i ers t o su o r t a u l t i aster co iur a t io a d to a oid da t a co t e - ti o ac oe addr data cs e cont rol adsp- addr control adsp- id reset clin adsp- cloc addr data sdram optional cs addr data id reset clin cont rol addre s s dat a cont rol addre s s dat a control adsp- id reset clin addr data e ras cas dm cl a ce cs data sde ras cas dm sdcl sda sdce br rd ms sbts cs ac br red hbg hbr r bms addr reset data addr data boot eprom optional global memor and peripherals optional host processor interface optional host processor itera c e te s h ar c m e lo d y u l t r a o st i t e r ace ea l e s e a sy co e c - tio t o s t a da r d - i t - i t o r - i t icr o r o ces s o r u s e s i t li t t le ad di t i o a l a r d a r e re u ir e d t e o st i t e r ace is a cce s s e d t r o u t e s h a r c m e lod y u l tra s et e r al o r t f o u r c a el s o dm a are a ai l a l e or t e o st i te r a c e c o d e a d d a t a t r a sers a r e acco li se d i t lo s o t a r e o er e ad te o s t r o c ess o r r e u es ts t e s h ar c m e lo dy u l t r a s et e r a l u s i t t e o s t u s re u e s t hb r o s t u s ra t hb g a d re a d y r e d s i a l s t e o s t c a d i re c t ly re a d a d r it e t e i ter a l i o p r e i sters o t e sh arc m e lo d y u l t r a ad ca ac c e ss t e d m a ca el s e t u ad e ss a e re i ste r s d m a s e t u i a a o st o u l d ea le i t t o access a y i ter a l e o r y addr es s ia d m a tra sers e c t o r i t e r r u t s u o r t r o ides e i cie t ee c u t io o o s t coa ds geeral-p u rose io ports t e sh a r c m e l o dy ult r a a l s o c o t ai s ro r a a l e e - eral- ur o s e io i s ta t c a u c tio as ei ter i u ts o r o u t u t s a s o u t u t s t es e i s ca si al e r i eral de ices as i u ts t es e i s ca r o ide t e t e s t o r co di t i o al r a c- i prora booti t e i te r a l e or y o t e sh a r c m e l o dy ult r a c a e o o t ed a t sys t e o e r - u r o ei t er a - i t ep r o m a o st ro c e s s o r t e spi i t e r a c e or t rou o e o t e l i o r t s s e l e c t i o o t e o ot s o u r c e i s c o t ro l l e d y t e b o ot m e or y se l e c t bms eb o o t ep r o m b o o t a d li h o s t b o o t lb o o t i s - - o r - i t o s t r o c ess o rs ca als o e us ed o r o o t i f i ure s ared m e o r y mult irocessi s y ste rev. 0 | page 11 of 28
adsst-sharc-melody-ultra poer sulies t e s h a r c m e l o d y u l tra a s se a r a t e o e r s u l y c o ec- ti o s o r t e i t e r al ddint e t e r al ddext ad a a l o a dd a gnd o e r s u lies te i t e r al ad a alo s u lies u s t e et t e r e u ir ee t t e et e r al su l y u s t e e t t e re u ire e t a l l e te r a l su ly i s u st e c o e c t e d to t e s a e su ly n o te t a t t e a a l o su ly a dd o e r s t e s h ar c m e lo d y u l t r a r o c ess o r s clo c e e ra t o r pll t o r o d u c e a st a le clo c r o ide a et e r al cir c ui t t o i l t er t e o e r i u t t o t e a dd i p l ace t e i l t er as clos e as o s s i le t o t e i f o r a ea - le cir c ui t s e e t o r e e t o is e cou li us e a ide tra c e o r t e a alo r o u d a gn d si al a d i stall a de- co u li c a a ci t o r as c l os e as o s s i le t o t e i f i ur e f i gure 8. a n a l og p o w e r (a v dd ) f i l t er circui t v ddint 10 0.1 p f 0.01 p f agnd av dd rev. 0 page 12 of 28
adsst -sharc-melody-ultra pin function descriptions te s h arc m e lo d y u l t r a i de i i t i o s ca e o u d i e i i o a e i u ts ide ti i e d as sy c r o o u s s u s t e e t t i i r e u i r e e ts i t r e s ec t t o c l i n o r i t r e s ec t t o t c o r t m s td i i u ts ide ti i e d as asy c r o - o us a ca e as ser t ed asy c r o o us l y t o clin o r t o t c o r trst t i e o r u l l u us ed i u ts to ddex t or g n d e c e t o r t e ol l o i t a le ad d r d a t a b r s t cl o ut n o t e ta t t es e i s a e a lo i c le e l o ld cir c ui t ea le d o t e s h arc m e lo d y u l tr a ds p i t i d pa a c rd r dm a r dm a g id n o t e t a t t es e i s a e a u l l - u ea le d o t e s h ar c m e lo d y u l tra ds p i t id lcl la c ld a t lp d r d e s e e t e l i p o r t bu er c o t r o l re i s t er bi t de i i t i o s i t e sh arc m e l o dy u l t r a d s p h a rd a re r e e re c e d a d b s c l s p i c l m i s o m o s i emu tm s trst td i n o t e t a t t es e i s a e a u l l -u top view 13 14 11 12 91 0 78 56 34 12 emu gnd tms tck trst tdi tdo gnd key (no pin) btms btck btrst btdi gnd f i gure 9. jt a g t a r g et bo ar d con n ec to r for jt a g equ i p p e d a n al og d e v i ces ds p (ju m pers i n p l ace ) top view 13 14 11 12 91 0 9 78 56 34 12 emu gnd tms tck trst tdi tdo gnd key (no pin) btms btck btrst btdi gnd f i gure 10. jt a g t a rget bo ar d con n ec tor with n o l o c a l b o undar y s c a n 0 . 24" 0. 8 8 " 0. 64 " f i gure 11. jt a g p o d c o nn ec tor d i me nsions 0.10" 0.15" f i gure 12. jt a g p o d conn ec tor k e ep - o ut a r ea rev. 0 | page 13 of 28
adsst-sharc-melody-ultra te ol l o i s y ols a e a r i t e t y e col u o t a l e ta le pi f u ct i o d e s c ri t i o a asycroous g groud i iut o outut p poer suly s sycroous ad actie drie o d oe drai t tree-state e sbts is asserted or e te sharc melody ultra is a us slae u l i e re i o u s sh a r c ro c e s s o r s t e sh a r c m e l o dy ult r a co t a i s i t e r al s e r i es r e sis t a ce e ui ale t t o o al l i - u to u t ut dr i ers ece t t e c l in a d xt a l i s t er eo r e o r t r aces lo er t a si i c es et e r al s e r i es r e sis t o r s o c o t ro l d a t a cl o c or r ae s y c i s are ot re u i r e d to da e r e l e c tio s r o tra sis sio li e e e c t s o r o i t-t o - o i t co e c t i o s h o e e r o r o r e co le e t o r s suc as st a r co iur a t io s s e r i es t e r ia t io is st i l l r e co e d e d m n e m o n i c t y p e f u n c t i o n ack i/o/s memory acknowledge . ex ternal devices can deas s e rt ack (l ow ) to add wait s t ates to an external memory access. ack is used by i/o devices, memory con t rollers , or other peripher als to h o ld off completi on of an external memory access. the sharc melody ultra deasserts ack as an output to add wait states t o a synchron ous ac cess of its iop re gisters. ack has a 20 k internal pull-up resi stor that is enabled d u ring reset or on dsps with id2C0 00x. a d d r 2 3 C 0 i / o / t external bus address . the sharc melody ultr a outputs addre sses for e x ternal memory and peripherals on these pins . in a multiproces s or system, the bus master outputs ad d r esses for re ad /writes of the iop registers of other sharc melody ultra process o rs, while all other inter n a l memory resou r ces can b e acce ssed indirectly via dma control (that is, accessing iop dma par a meter registers ) . t h e sharc melod y ultra inputs ad d r esses when a h o st pro c esso r or multip roces s ing bus m a ster is read ing or writing its iop registers. a keeper latch o n the dsps addr23C0 pins maint a ins the input at the level to whi c h it was la st driven. this latch i s only enabled on the sharc melody ultra with id2C0 00x. a g n d g analog power supply return. av dd p analog power supply . nominally 1.8 v dc and supplies the d s p s internal pll (clock generator). this pin has the same specification s as v ddin t , ex cept that added filtering circuitr y is required. see the power supplie s section. bms i/o/t boot memory s e lect . serves as an output or input as selected with the eboot and lboot pins s e e on page 18. this input is a system configuration sele ction that should be hardwired. for host and eprom boot, dma channel 10 (epb0) is used. for link boot and spi boot, dma channel 8 is used. t h ree-state only in eprom boot mode (when bms is an output). b m s t r o bus master out p ut . in a multiprocess or system, ind i cates whet h e r the sharc melody ultra is current bus master of the sh ared external bu s. the sharc melody ul tra d r ives bm st r high only whi l e it is the bus master. in a single-processor system (id 000), the processor drive s this pin high. br 6C1 i/o/s multiprocessing bus reque s ts . used by multiprocessing sharc melody ultra proces sor s to ar bitrate for bus mastershi p . a sharc m e lod y ul tra only d r ives its own br x line ( c or respo n d i ng to the value of its id2C0 inputs) and monitors al l others. in a multiproce ssor syst em w i th less tha n six s harc m e lod y ul tra proces sors, the unused br x pi ns should be pu lled high the pr ocess o rs o w n br x line must not be pulled high or l o w because it is an output. b r s t i / o / t sequentia l bur s t access . brst is asserted by s harc melody ul tra to indicate t h at da ta associ a t ed with conse c utive ad dresse s is being r e ad or written. a slave d evice s a mple s the initial ad d r ess and i n crements an internal address counter after each transfer. the incremented address is not pip e lined on the bus . a master sharc melody ultra in a multiprocessor envir o nment ca n read slave e x ternal port buffers (epb x) using the burst protoco l . brst is asserted after the initial access of a burst transfe r. it is asserted for every c y cle after that, ex cept for the last data reques t cycl e (denoted by rd or wr assert ed and brst ne gated). a keeper latch on the dsps brst pin maintain s the input at th e level to whi c h it was la st driven. this latch is o n ly enab led on the sharc melody ultra with id 2C0 00x. cas i/o/t sdram colum n access strobe. in conjunctio n with ras , ms x, sdwe , sdclkx, and someti mes sda10, defines the oper a tion for the sdram to perform. t a b l e 3 rev. 0 page 14 of 28
adsst -sharc-melody-ultra m e o i c t y e f u c t i o c l c f g i coreclin ratio cotrol sha r c mel o dy ul tra core cl oc is tructio cycle rate is e ual to n plliclk where n is user selectable to 2, 3, or 4, using the clkcfg1C0 inputs. these pins can also be use d in combin ation wi th the clkdbl pin to generate additional core c l ock r a tes of 6 clkin and 8 clkin (s ee the clock rate ratios table in the clkdbl de scription). clkdbl i crystal double mode enable. this pin is used to enable the 2 cloc k double circuitry, where clkot can be configured as either 1 or 2 the rate of clkin. this clkin double circuit is primarily intended to be used for an ex ternal crystal in con unction with the internal clock generator an d the xta l pin. the internal clock generator, whe n used in conu n ction wi th the xt al pin and an external crysta l, is designed to support up to a max imum of 25 mh ex ternal crystal freq uency. clkdbl can be used in xtal mode to g e nerate a 50 mh input into the pll. the 2 clock mode is enabled (d uring reset low) by tying clkdbl to gn d, otherwise it i s connected to v ddex t for 1 clock mode. for exam ple, this en ab les the use of a 25 mh crystal to enable 100 mh core clock rates and a 50 mh clkot operati on whe n clkcfg1= 0, clkcfg1= 0, and clkdbl = 0. this pin can also be used to generate different cl ock rate r a tios for extern a l cloc k osc i ll ator s. t h e poss i ble clock r a te ratio options (up to 100 mh) for either clkin (external clock oscillator) or xta l (crystal input) are as foll ow s clock rate rati os clkdbl c l k c f g 1 c l k c f g 0 core c l k i n c l k i n c l k o t 1 0 0 2 1 1 1 0 1 3 1 1 0 1 0 4 1 1 0 0 0 4 1 2 0 0 1 6 1 2 0 1 0 8 1 2 an 81 ratio enables the use of a 12.5 mh crysta l to ge nerate a 100 mh core (instruction clock) rate and a 25 mh clkot (external port) clock r a te. see figure 13. note that when using an ex ternal crystal, the max imum crystal f r eq ue ncy cann o t exceed 25 mh. for all other externa l cl ock source s, the maximum clkin frequency is 50 mh. c l k i n i local clock in . sed in con unction with xtal. clkin is the sh arc melody ltr a clock input. it configures the sharc melody ltra to use either its internal clock ge nerator or an external cl ock source. connecting the necessary components to clkin and xtal enables the internal clock gene rator. connecting the external clock to clkin while l e aving xtal unconnected configures the sharc melody ltra to use the external c l oc k source such a s a n external c l oc k os cillator.the s harc melody l tra extern al port cycles at the frequency of clkin. the instruction cycle rate is a multiple of the clkin frequency it is progr a mmab l e at po wer-up via the clkcfg1C0 pins. clkin may not be halted, change d, or operated below the specified freq uency. c l k o t o / t local clock ou t. clkot is 1 or 2 and is driven at either 1 or 2 the freq uency of clkin fre q uency by the current bus master. the frequency is determined by the clkdbl pin. this output is three-stated when the sharc m e lod y ltra is not the bus master or w h en the host co ntrols the bus ( h bg asserted). a keeper latch on the dsps clkot pin maint a ins the output at the level to which it was last driven. this latc h is only enabled on the sharc melody ltra with id2C0 = 00x. if clkdbl enab led , clkot = 2 clkin if clkdbl d i sabl ed , clkot = 1 clkin note that clkot is controlled only by the clkdbl pin and operates at either 1 clkin or 2 clkin. do not use clkot in multiprocessing systems use clkin instead . cs i/a chip select. asserted by host processor to s e lect the sha r c mel o dy l tra. d a t a 4 7 C 1 6 i / o / t external bus data . the sharc melody ltra inputs and output s data and instruct ions on these pins. pull-up resistor s on unused d a ta pins ar e not necessary. a keeper latch on th e dsps data47C16 pins maintains the input at the level to which it wa s last driven. this latch is on ly enabled on the sh arc melody ltr a with id2C0 = 00x. note that da ta [158] pins (mult i plexed with l1data[70 ]) can also be used to ex tend the data bus if the link ports are disa bl ed and will not be used. in addition, da ta[70 ] pins (mul tipl ex ed w i th l0dat a [ 7 0]) can al s o be used to ex tend the data bus if the link ports are not used. this enables e x ecu t ion of 48-bit instructions from external s b sram (system clock speed-external p o rt), sram (system clock speed-extern a l port) and sdram (core clock or on e-ha lf the core cl ock s p eed). the ipackx instruction pa cking mode bits in sscon should be set co rrectly ( i pack1C0 = 0x1) to enable this full instru ction width/no- p acki ng mode of operation. rev. 0 page 15 of 28
adsst-sharc-melody-ultra m n e m o n i c t y p e f u n c t i o n dmag1 o/t dma grant 1 (dma channel 11). asserted by s harc melody ul tra to indicate t h at the req u ested dma starts on the next cycle. driven by bus master only. dmag1 has a 20 k? internal pull-up re sist or that is enab le d for dsps with id2C0 = 00x. dmag2 o/t dma grant 2 (dma channel 12). asserted by t h e sharc melo dy ultra to indic a te that the req u ested dma starts on the ne xt cycle. driven by the bus master only. dmag2 has a 2 0 k? internal pu ll-up resi stor tha t is enabled for dsps with id2C0 = 00x. dmar1 i/a dma req u est 1 (dma channel 11). asserted by external port devices to request dma services. dmar1 ha s a 20 k? internal p u ll-up resistor th at is enabled for dsps with id2C 0 = 00x. dmar2 i/a dma req u est 2 (dma channel 12). asserted by external port devices to request dma services. dmar2 ha s a 20 k? internal p u ll-up resistor th at is enabled for dsps with id2C 0 = 00x. d q m o / t sdram data m a sk. in write mo d e , dqm has a latency of zero a n d is used durin g a precharge c o mmand and during sdram power-up in itial i zation. d x a i / o data tr ansmit or receive cha nnel a ( s erial p o rts 0, 1, 2, 3) . ea ch dxa pin ha s an internal pull- up resistor. bidirectional da ta pin. this sign al can b e config ured as an output to transmit serial data, or as an input to receive seri al data. d x b i / o data tr ansmit or receive cha nnel b (serial ports 0, 1, 2, 3). ea ch dxb pin h a s an internal pull-up resistor. bidirectional da ta pin. this sign al can b e config ured as an output to transmit serial data, or as an input to receive seri al data. eboot i eprom boot s e lect . for a desc ription of ho w this pin o p erates , s e e o n page 18. t h is si gnal is a system configuration sel e ction that should be h a rd wired . emu (o/ d ) emulation stat us . mus t be connected to the s harc mel o dy ul tr a analog devi ces dsp t ools p r oduct line of jt ag emulators target boa rd connector on ly. emu has an intern al p u ll-up resistor. f l a g 1 1 C 0 i / o / a flag pins . each pin is co nfigured via control bit s as either an input or output. a s an inp ut, it can be tested as a condition. as an output, it can be us ed to signal external periph erals. f s x i / o transmit or re ceive frame sync ( s erial ports 0, 1, 2, 3) . t h e frame sync puls e initiates shifting of serial d a ta. this signal i s either genera ted internally or e x ternally. it can be active high or lo w or an ear l y or late frame sync, in referenc e to the shifting of serial data. g n d g power supply return (26 pins). hbg i/o host bus grant . acknowledges an hbr bus req u est, indicating that t h e host pro c ess o r may take con t rol of the external bus. hbg is asserted ( h el d low) by th e sh arc melody ultr a until hbr is release d . in a multiprocessing system, hbg is output by the s harc melody ultra bus master and is monitored by all others. after hbr is asserted, and before hbg is given, hbg will fl oat for 1 t ck (1 clki n cycle). to avoid erroneous grants, hbg should be pulled up wit h a 20 k? to 50 k? external re si stor. hbr i/a host bus req u est . must be ass e rted by a host proces sor to request control of the sharc melody ultra proces sor s exte rnal bus. whe n hbr is asserted in a multiprocessing sy stem, the sharc melody ultr a that is bus master wil l r e linquis h the bus and assert hbg . t o relinqui sh the b u s, the sharc melody ultra places the ad d r ess, d a ta, select, and strob e lines in a h i gh imped ance stat e. hbr has priority o ver all sharc m e lod y ultra bus requests (br 6C1) in a multiprocessing system. i d 2 C 0 i multiprocessing id. determines which multipr o cessing bus re quest (br 6C1) is us ed by the sha r c melody ultra. id = 001 corresponds to br1 , id = 010 corresponds to br2 , and so on. use id = 000 or id = 001 in single- proces sor syste m s. t h ese line s are a system co nfigur ation sele ction that shoul d be hard wired or only changed at rese t. irq 2C0 i/a interrupt request lines. these pins are sample d on the rising edge of clkin an d may be either edge- triggered or level-sen sitive. lboot i link boot. for a description of h o w this pin oper a t e s , s e e o n p a g e 1 8 . t h is signal i s a syst em configuration se lection that sho u ld be hard wire d . l x a c k i / o link port acknowledge (link ports 0C1). each lxack pin has an in ternal pull -down 50 k? resist or that is enabled or disabled by the lxpd rde bit of the lctl register. l x c l k i / o link port clock ( l ink ports 0C1) . each lxclk pin has an intern al pull-d o wn 50 k ? resistor that is enabled or disabled by the lxpdrde bit of t h e lctl register . t a b l e 3 t a bl e 3 rev. 0 | page 16 of 28
adsst -sharc-melody-ultra m n e m o n i c t y p e f u n c t i o n lxdat7C0 [data15C 0] i/o [ i /o/t ] link port data (link ports 0C1). for silic o n revi si ons 1.2 and hig h er, each lxdat pin has a k eepe r latch that is en abled whe n use d as a d a ta pin, or a 20 k? internal pul l -do w n resi stor that is enab le d or disabled by the lxpdrde bit of the lctl register. for silicon revi si ons 0.3, 1.0, and 1.1, each lxdat pin ha s a 50 k? internal pul l -do w n resi stor that is enab led or disabled by the lxpdrde bit of t h e lctl register . note that l1da ta[7:0 ] are mult iplexed with the data [15:8] pin s ; l0data[7:0 ] a r e mul t ipl e x e d w i th the data[7:0 ] pins . if l i nk ports are dis a bl ed and are not be used, these pins c a n be u s ed as additiona l data lines for ex ecuting instructions at up to the full clock rate from extern al memory. see data47C16 for more information. miso i/ o (o/ d ) spi master in sl ave out. if the sharc melody ul tra is configured as a master, the miso pin beco mes a data receive (input) pin. if the sharc melody ultra is config ured as a slave, the miso pin becomes a data transmit (output ) pin. in a sharc melod y ultra spi interc onnection, the data is shifted out fr om the m i s o output pin of the slave and shifted into the m i so inp ut pin of the master. m i so has an intern al pull-up resi stor. m i so can be configured as o/ d by setting the opd bit in the spictl register. note that only one slav e is ena b l e d to transmit d a ta at any given time. m o s i i / o (o/ d ) spi master out slave in. if the sharc melody ul tra is configured as a master, the mosi pin beco mes a data transmit (outpu t ) pin. if the sh a r c mel o dy ul tra is configured as a slave, the mo si pin become s a data receive (input) pin. in a sharc m e lody ultra spi interco nnection, the data is shifte d out from the mosi output pin of the master and shifted int o the mosi input(s) of the slave( s) . m o si has an i n ternal pul l -up resistor. ms 3C0 i/o/t memory select lines. t h ese outputs are assert ed ( l ow) as chip selects for the c o rresp ond i ng b a nks of external mem o r y . memory bank sizes are fixed to 16 mw ords for non-sdram and 64 mw ords for sdram. the ms 3C0 outputs are decoded memory addres s l i ne s. in asynchro nou s acces s mode, the ms 3C0 outputs transition with t h e other address outp uts. in synchronous acces s mod e s, the m s 3C0 outputs assert with the other ad d r ess li nes; ho wever, t h ey d e -assert after the fi rst clkin cycle in which ack is sampl e d asserted . in a multiproces s or systems, the m s x si gnals are trac ke d by slave sharcs. t h e internal ad d r esses 24 an d 26 are zeros and 26 and 27 are decode d into ms 3C0. n c do not connect. reserved pins that must be le ft open and unconnected (5 pins). pa i/o/t priority access. asserting its pa pin enables a sharc melody ultra bu s slave to int e rrupt backgrou nd dma transfers and gain access to the ex ternal bus. pa is connected to all sharc me lod y ultra proce ssor s in the system. if access priority is not required in a system, the pa pin shou ld be left unconnected. pa has a 20 k? internal pul l -up resistor that is e n abled for dsps with id2C0 = 00x. ras i/o/t sdram row ac cess strobe. in conjunctio n wit h cas , ms x, sdwe , sdclkx, a n d sometimes s d a10, this pin defines the oper a tion for the sdram to perform. rd i/o/t memory read strobe. rd is asser t ed whenever the sharc melody ul tra reads a word from exter n al memory or from the iop registers of other sharc melody ultr a processors. external devices, including ot her sharc melody ultra processors, must assert rd for readin g a word of the sharc melody ultra iop register memory. in a multiprocessing system, rd is driven by the bus master. rd has a 20 k? internal pull-up resi stor that is enabled for dsps with id2C0 = 00x. redy o (o/ d ) host bus ackn owledge. the sharc mel o dy ul tra deas s e rts redy (l ow ) to ad d wait states to a host acce ss of its iop registers when cs and hbr inputs are asserted. reset i/a processor reset. resets the sharc melody ultr a to a known sta t e and begins e x ecution at the program memory location specified by the hard ware re set vector address. the reset input must be asserted ( l ow) at power-up. r p b a i / s rotating priority bus arbitrati o n select . when rpba is high, rotating priority for multiproce ssor bus arbitration is sel e cted. when rpba is low, fix e d priority is sele cted . t h is signal is a system config uration selectio n that must be set to the same value o n every sharc melody ultra. if the value of rpba is changed during system operation, it must be changed in the same clkin cycle on every s harc melody ul tra. rstout o reset out. when rstout is asserted (low), this pin in dicates that the core blocks ar e in r e set. it is d e asse rted 4096 cycles after reset is deasserted indicating that t h e pll is stable and locked. (rstout exists only for silic o n revis i on 1.2.) sbts i/s suspend bus a n d three-st ate . external devices can assert sbts (l ow ) to pl ace the ex ternal bus addres s , d a ta, selects, an d strobes in a hi gh imped ance s t ate for the following cycle. if the sharc melod y ultra attempts to access ex te rn al me mory while sbts is as serted , the proc essor will h a lt a n d the memory acces s will n o t be com p leted until sbt s is deasserted. sbts should only be used to recover from host process o r/ sharc mel o dy ul tra deadl o ck. rev. 0 page 17 of 28
adsst-sharc-melody-ultra m n e m o n i c t y p e f u n c t i o n s c l k x i / o transmit/receive seria l clock (serial ports 0, 1, 2, 3). each sclk pi n has an inter n al pull-up resistor. this signal c a n be eit h er internally or externally gener a ted. s d a 1 0 o / t sdram a10 pi n. enables applications to refresh an sdram in paral l el w i th a n o n-sdram accesses o r host acces s es. s d c l k 0 i / o / s / t sdram clock output 0. clock for sdram devi ces. s d c l k 1 o / s / t sdram clock output 1. additional c l oc k for sdram devices. for sy stems wit h multiple sdram d evices, this pin handle s the increased clock load requiremen ts, el iminating t h e need for off-chip clock buffe rs. either sdclk1 or both sdclkx pins c a n be three-state d . s d c k e i / o / t sdram clock e n able. enable s and d i sable s the clk signal. for d e tails, see the d a ta sheet supp lied with the sdram device. sdwe i/o/t sdram write e n able. in conju n ction with cas , ras , ms x, sdclkx, and sometimes sda10, this pin defines the operation fo r the sdram to perform. spiclk i/o serial peripher al interface c l ock signal. drive n by the master, this signal controls the rate at which data is transferred. the master may transmit data at a variety of baud rat e s. spiclk cycles o n ce for each bit trans mitted. spi c lk is a gated clock that is active during data transfers, only for the length of the transferred word. slave devi ces igno re the serial clock if the slave select in p ut is driven inactive (high). spiclk is used to shif t out and shift in the data driven on the miso and mosi l i nes . the data is always shifted out on one clock edge of the clock an d samp led on the opp osite edge of the clock. cloc k polar ity and clock pha s e relativ e to data are programma b l e int o the spictl co ntrol register an d define the transfer format. spiclk has an in ternal pull-up re sistor. spids i serial peripher al interface sl a v e d e vice se lec t . an active low signal used to e n able slav e d evices. t h is input signal be h a ves li ke a chi p select, and is pr ov ided by the m a ster device for the slave device s. in multimaster mode, spids signal can b e asserted to a master d evi ce to signal that an error has occurr ed because some other device is also tryi ng to be th e master device. if assert ed low when the devic e is in master mode, it is consi d ered a multim aster error. for a si ngle-ma s ter, multiple-s lave c o nfiguration wh ere flag3C0 are used, this pi n must be tied or pulled high to v ddex t on the ma ster device. for sharc melody ultra to sharc melody ultra spi interaction, any of the master sharc melody ultra processors flag3 C 0 pins can be used to drive th e spids signal on the sharc melody ultra spi slave device. tck i test clock (jtag). provides a clock for jtag boundary scan. t d i i / s test dat a input (jtag). provides serial data for the boundary sc an logic. tdi has a 20 k? internal pull-up resistor. t d o o test dat a outp ut (j tag). serial scan output of the boundary sc an path. time x p o timer expired. asserted for four core clock cy cles when the tim e r is enab led. t m s i / s test mode se le ct ( j t a g) . used to control the tes t state machine. t m s has a 20 k? internal pull-u p resistor. trst i/a test reset (j ta g). resets the te st state machine. trst must be asserted ( p ulsed low) after power-up or held low for pr oper o p eration of the sharc melody ultra. t r st has a 20 k ? internal pull-u p resistor. v ddin t p core power supply . nominally 1.8 v d c and supplie s the dsps core proc ess o r ( 14 pins) . v ddex t p i/o power supply. nominally 3.3 v dc (13 pins). wr i/o/t memory write low strobe. wr is asserted when t h e sharc melody ul tra writes a word to ex ternal memory or the iop registers of other sharc m e lod y ultra proces sors . external d evice s m u st assert wr for writing to the sharc m e lod y ultras iop registers. in a multiproce ssing syst em, wr is driven by the bus master. wr has a 20 k? internal pull-up resi stor that is enabled f o r dsps with id2C0 = 00x. x t a l o crystal oscillat o r terminal 2. used in conjunction with clkin to enable the sharc melody ultr as internal clock osci llator or to disable it to us e an extern al clo c k source. see clkin. boot m o de s table 3. boot mode selection eboot l b o o t bms bootin g mod e 1 0 output eprom (connect bms to eprom chip select). 0 0 1 (input) host processor. 0 1 0 (input) serial boot via spi. 0 1 1 (input) link port. 0 0 0 (input) no booting. proc essor executes from external m e mory. 1 1 x (input) reserved. rev. 0 | page 18 of 28
adsst -sharc-melody-ultra specifications recommended operat ing c o ndi t io ns tale c grad e k grade p a r a m e t e r test condition s m i n m a x m i n m a x u n i t v ddin t internal (core) supply voltage 1.71 1.89 1.71 1.89 v av dd analog (pll) su pply voltage 1.71 1.89 1.71 1.89 v v ddex t external (i/o) supply voltage 3.13 3.47 3.13 3.47 v v ih high level input voltage 1 @ v ddext = max 2.0 v ddex t + 0.5 2.0 v ddex t + 0.5 v v il low level input voltage 1 @ v ddext = min C0.5 0.8 C0.5 0.8 v t case case operating temperature 2 C40 +105 0 +85 c 1 appli e s t o i n put a n d bi di rect i o nal pins: dat a 47C 16, addr23C0, ms 3C0, rd , wr , ack, sbts , irq2C0, fl ag11C0, hbg , hbr , cs , d mar 1 , d mar 2 , br 6C1, id2C0, r p ba, pa , brst, fs x, dx a, dxb , s c lkx, ra s , cas , sdwe , sd clk0, lxd a t7C0, lxcl k, lxack , s p i c lk, mo si, miso, spids , eboot, l b oot, bms , sd ck e, clk _cfg x, clkdbl , cl kin, re se t , trst, t c k, t m s, t d i. 2 see t h e th s e c t io n on page 24 fo r in f o rmat ion on t h e rmal sp ecificat ion s . ermal c h aract e rist i c s rev. 0 | page 19 of 28
adsst-sharc-melody-ultra electrical character i stics tale p a r a e t e r test coditio s m i m a u i t oh hi leel outut oltae ddext i i oh a ol lo leel out ut oltae ddext i i ol a i ih hi leel iut curret ddext a in dde x t a a i il lo leel iut curret ddext a in a i ihc clin hi le e l iut curret ddext a in dde x t a a i ilc clin lo leel iut curret ddext a in a i ih eeer hi load curret ddext a in a i il eeer lo load curret ddext a in a i ih-od eeer hi o erdrie curret ddext a a i il-od eeer lo oe r drie curret ddext a a i ilpu lo leel iut curret pull-u ddext a in a i o h tree-state leaae curret ddext a in dde x t a a i o l tree-state leaae curret ddext a in a i o lpu tree-state leaae curret pull-u ddext a in a i o lpu tree-state leaae curret pull-u ddext a in a i o hpd tree-state leaae curret pull-do ddext a in dde x t a a i o hpd tree-state leaae curret pull-do ddext a in dde x t a a i dd-in pea suly curret iteral t ccl s ddin t a a i dd-in high suly curret iteral t ccl s ddin t a a i dd-in lo suly curret iteral t ccl s ddin t a a i dd-idle suly curret idle t ccl s ddin t a a ai dd suly curret aalo a dd a a c in iut caacitace in m h t case c in f ali e s t o out ut a d i di rect i o al i s data addr ms rd r ac d m flag hbg re d d mag d mag br bmst r pa brst fs da db sc l ra s cas sde sd a ld a t lcl l ac s p i c l mo si miso bms s d cl sd c e emu x t al td o clout timex p rstout see t e out sect io o ae o r t y i cal drie curr e t caailit i es ut dri e cu rre t s alies to iut is data addr ms sbts ir fl ag hbg hbr cs br id rpb a brst fs d a db s c l ra s cas sde sd cl l d a t lcl l ac s p i c l mo si miso spids eboot lboot bms sd c e cl cf g cldbl tc re se t clin a l ie s to iut is it ite ral ul l - u s rd r ac d mar d mar pa trst tms tdi ali e s t o cl in o ly alies to all is it eeer latces addr dat a ms brst cl out curret reuire d t o sitc ro et i to lo or r o et lo to i c aracte ri e d ut o t te s t e d ali e s t o t r ee- st a t a le i s data addr ms clout fl ag red hbg bms br - ra s cas sde d m sd cl sd ce sd a br st a l ie s to tree -statal e is it ul l - us rd r d mag d mag pa a l ie s to tree -statal e is it ite r a l u ll- u s d a d b s c l s p icl emu mi so mosi a l ie s to tree -statal e is it ite ral ul l - do s ld a t elo r e i si o l cl la c us e i o hpd or re a d ier a l ie s to tree -statal e is it ite ral ul l - do s ld a t r e is io ad ie r te tes t rora us ed to eas ure i dd -in pea rer es e t s o rst - c ase roc es sor oerat io a d is o t sust ai al e uder oral al icatio co d itio s a c tual i te ral oer ea s ureets ad e us i tyical al icat i o s a r e l e s s t a seci i e d f o r o re i o r a t i o see t e p sec tio o ae o e r d i ssi a t i o p o er diss i ati o p o e r dis siat i o po e r d i s s i a t i o curret uers are or ddin t a d a dd sul ie s co i e d i dd-in hig h is a coos ite aerae ased o a ra e o i actiity co d e se e te s e ctio o ae i dd-in l o is a co os ite aerae ased o a ra e o l o act i it y code se e t e sect io o ae idle de o t e s s h a r c m e l o dy ult r a st a t e duri eecut i o o id le i st ruct i o se e t e sect i o o a e c arac te ri e d ut o t te s t e d ali e s t o a l l si a l i s guara te e d ut o t te s t e d rev. 0 page 20 of 28
adsst -sharc-melody-ultra absolute maximum ratings timing spe c ific ations table 6. p a r a m e t e r r a t i n g internal (core) supply voltage (v ddin t ) C0.3 v to 2.2 v analog (pll) su pply voltage (av dd ) C0.3 v to 2.2 v ex ternal (i/ o ) suppl y vol t age (v ddex t ) C0.3 v to 4.6 v input voltage C0.5 v to v dde x t 0.5 v output voltage swing C0.5 v to v dde x t 0.5 v load capacitance 200 pf storage temperature range C65c to 150c the s h ar c m e lo d y u l t r a p r o c es s o r s in t e r n al clo c k s w i t ch es a t hig h er f r e q uen c ies t h a n t h e sys t em i n p u t clo c k (clkin). t o g e n e r a t e t h e in ter n al clo c k, t h e p r o c es s o r us es a n in t e r n al phas e-lo ck e d lo o p (p ll). this p ll bas e d c l o c kin g minimizes th e sk e w be tw e e n t h e sys t e m c l o c k (clki n ) sig n al a nd t h e p r oc e s so r s in t e rn al c l oc k ( t h e c l oc k so u r c e f o r th e e x t e rn al po r t lo g i c a n d i/ o p a ds). the s h ar c m e lo d y u l t r a p r o c es s o r s in t e r n al clo c k (a m u l t i p le o f clkin) p r o v ides t h e clo c k si g n a l fo r t i min g in ter n a l m e m- o r y , p r o c es s o r c o r e , link p o r t s, s e r i al p o r t s, a nd ext e r n al p o r t (as re qu i r e d f o r re a d / w r i te st ro b e s i n a s y n ch ronou s a c c e ss mo d e ) . d u r i n g r e s e t, p r og ra m t h e r a t i o b e tw e e n t h e p r o c es s o r s in t e r n al c l oc k f r eq ue n c y a n d e x t e rn al (cl k in ) c l ock f r eq ue n c y w i t h th e clk_cfg1 C0 and clkd bl p i n s . e v e n th o u gh th e i n t e rn a l clo c k is t h e clo c k s o ur ce fo r t h e ext e r n al p o r t , i t b e ha v e s as de- scri be d o n t h e cloc k r a t e r a tio c h a r t i n th e clkd bl pin des c r i p t io n in . t o de ter m i n e s w i t chi n g f r e q uen c ies fo r t h e s e r i a l an d l i n k p o r t s, divi de do wn t h e i n ter n a l clo c k usin g th e p r ogra mmab l e d i vider co n t r o l o f eac h p o r t (d ivx f o r th e se ri al po r t s a n d l x c l k d f o r th e l i nk po r t s ) . s t r e s s es g r e a t e r t h a n t h os e lis t e d a b o v e ma y c a us e p e r m a n e n t da ma g e t o t h e de v i ce . th es e a r e s t r e s s ra t i n g s on l y f u n c t i o n al op e r a t i o n of t h e d e v i c e a t t h e s e or an y ot he r c o nd it i o n s g r e a te r t h a n t h os e i n di c a t e d i n t h e o p er a t io na l s e c t io n s o f t h is sp e c if i- c a t i o n i s not i m pl i e d. e x p o su re to ab s o lute m a x i m u m r a t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vi ce r e liab i l i t y . t a b l e 2 ep: multiprocessing host sram sbsram ratios u 2, u 3, u 4 link port: u 1, u 1/2, u 1/3, u 1/4 by sw core io-processor ep: sdram u 1/2, u 1 by sw clkout lclk1:0 sdclk1:0 cclk (33.3mhz to 100mhz) plliclk (8.4mhz50mhz) clk_cfg1:0 clkdbl clkin (4.2mhz50mhz) xtal uart crystal or crystal oscillator clock doubler u 1, u 2 pll f i g u re 13. co r e c l o c k and sy s t em r e l a t i ons h ip t o clki n rev. 0 page 21 of 28
adsst-sharc-melody-ultra power diss ipatio n t o tal p o w e r dissi p a tion has two co m p on e n ts: o n e d u e t o in t e r n al cir c ui t r y a n d one d u e to t h e s w i t chi n g o f ext e r n al o u t p ut dr i v ers. i n ter n a l p o w e r d i ssi p a t ion de p e n d s on t h e in st r u c t io n exe c u t io n s e q u e n ce a nd t h e da t a o p er a n ds in volve d . u s in g t h e c u r r e n t sp e c if ic a t io ns (i dd- inp e a k , i dd - i n h ig h , i dd- inl o w , i dd - i dle ) f r o m th e ( o n p a g e 20), t h e p r og ra mm e r ca n es t i ma t e t h e sh arc m e l o d y u l t r a pro c e s s o r s i n te r n a l p o we r s u pp l y ( v ddint ) in p u t c u r r en t fo r a sp e c if ic a p plic a t io n, acco r d i n g to t h e fol l o w in g fo r m u l a: a t y pi c a l p o we r c o ns u m pt i o n c a n now b e c a l c u l a t e d f o r t h e s e co ndi t i on s b y addin g a ty pica l i n ter n a l p o w e r d i ssi p a t ion: p to t a l = p ex t + p int + p pl l e l ec tr ical c h a r ac t e r i s t i c s e l ec tr ical cha r ac t e r i s t i c s t a b l e 5 t a b le 5 w h er e p p ll is ai dd 1.8 v , usin g th e val u e f o r ai dd lis t e d in t h e ( o n p a g e 20). output drive currents f i gur e 1 4 f i gure 14. t y pic a l d r ive cu rrents s h o w s typ i cal i - v c h arac t e r i s t ics f o r th e o u t p u t dr i v - ers o f t h e s h a r c m e lo d y u l t r a . the c u r v es r e p r es en t t h e c u r r en t dr i v e ca p a b i li ty o f t h e ou t p ut dr i v ers as a f u n c t i on o f out p ut vol t ag e. i ddi n t = % pe a k i dd - i n p e a k + % hi g h i dd - i n h ig h + % lo w i dd - i nlo w + % id l e i dd - i dl e load v d d ext curre nt ma source v ddext voltage v v ddext = v c v ddext = v +c v ddext = v +c v ddext = v +c v ddext = v +c v ddext = v c the ext e r n al com p on e n t o f t o t a l p o w e r dis s i p a t io n is c a us e d b y t h e s w itch i n g of output pi ns . i t s m a g n itu d e d e p e nd s o n x the n u m b er o f o u t p u t p i n s tha t swi t ch d u r i n g e a c h c y c l e ( o ) x the max i m u m f r e q uen c y a t w h ich t h e y can s w i t ch ( f ) x their lo ad c a p a ci t a n c e ( c ) x their v o l t a g e s w i n g ( v dd ) a nd is ca lc u l a t e d b y p ex t = o c v dd 2 f the lo ad c a p a ci t a nce sh o u ld i n cl ude t h e p r o c ess o r p a cka g e ca p a c i tan c e (c in ). th e s w i t ching f r e q uen c y in cl udes dr i v i n g t h e lo ad hig h and t h e n b a ck lo w . a ddr ess and d a t a p i n s c a n dr i v e hig h and lo w a t a max i m u m ra te o f 1/t ck wh ile w r i t in g t o a n sdr a m me mo r y . test co ndi t io ns out p ut enabl e tim e ou t p u t p i n s a r e co n s i d e r ed t o b e e n a b l e d w h en th ey h a v e ma d e a tra n si ti o n f r o m a hi gh im p e da n c e s t a t e t o th e po i n t w h en th e y s t a r t dr i v in g. th e o u t p ut ena b l e t i m e , t en a , is t h e in ter v a l f r o m t h e p o i n t w h e n a re f e re nc e s i g n a l re a c he s a h i g h or l o w vo lt age le v e l t o t h e p o in t w h en t h e ou t p u t has r e ach e d a s p e c if ie d hig h o r lo w tr i p p o in t, as sh o w n i n . i f m u l t i p le p i n s (s uc h as t h e da t a b u s) a r e ena b le d , t h e m e as ur e m en t v a l u e is t h a t o f t h e f i rst pin t o st a r t dr i v i n g. ex a m p l e : es tima te p ext wi th t h e f o llo w i n g a s s u m p ti o n s: f i gur e 1 5 i g u r e 1 5 x a sys t em wi th on e b a n k o f ext e r n al m e m o r y (32 b i t) x t w o 1m 16 s d ram c h i p s a r e us ed , eac h wi t h a lo ad o f 1 0 p f (i gn o r i n g tra c e c a pa ci ta n c e ) out p ut disabl e tim e x e x t e r n al da t a mem o r y wr i t es can o c c u r e v er y c y cle a t a ra t e o f 1/t ck , wi t h 50% o f the p i n s s w i t chin g ou t p u t p i n s a r e co n s i d e r ed t o b e d i sa b l e d w h en th ey s t o p d r i v - in g, go in to a hi g h im p e dan c e st a t e, a nd st a r t to de c a y f r o m t h eir o u t p u t hig h o r lo w v o l t a g e. th e t i m e fo r t h e v o l t a g e on t h e bu s t o d e c a y by ? v is dep e n d en t o n t h e c a p a ci t i v e lo ad , c l , a nd t h e lo ad c u r r en t , i l . this de ca y t i me can b e a p p r o x ima t e d b y t h e eq ua ti o n x the b u s c y c l e tim e is 50 m h z x the ext e r n al s d ram c l o c k ra t e is 100 mh z x s d r a m r e f r es h c y cles a r e ig n o r e d x a ddr es s e s a r e i n cr e m en t a l and o n t h e s a m e p a g e l l decay i v c t ' the p ex t eq u a tio n is calc u l a t e d f o r eac h c l as s o f p i n s tha t can dr ive. the o u t p u t dis a b l e t i m e , t dis , is t h e dif f er en ce b e tw e e n t meas ure d a nd t deca y , a s s h o w n i n f . t h e t i m e t meas ured is t h e rev. 0 page 22 of 28
adsst -sharc-melody-ultra i t e r al r o e te r e e r e c e si al s i t c es t o e t e outut o lt a e d e c a y s r o t e e a s u r e d outut i or out ut l o ol t ae t deca is calc u l a t e d i t t e st lo ads c l a d i l a d i t e ual t o eal e sys t e hol d ti e c a lc ulatio t o deter i e t e da t a o u t u t old tie i a a r t ic u l a r sys t e i r s t c a l c u l a t e t de c a usi t e e ua t i o i e r eio us l y c o o s e t o e t e di er e ce e t e e t e sh ar c m e lo d y u l t r a r o c es s o r s o u t u t o l t a e a d t e i u t t r e sold o r t e de i ce r e u ir i t e old t i e a ty i ca l i l l e c l is t e t o tal u s ca a ci ta c e e r da ta l i e a d i l is t e t o tal le aa e o r t r e e-s t a t e c u r r e t er da t a li e t e o ld t i e i l l e t deca l us t e i i u dis a l e t i e reference signal t dis output starts driing oh measured t measured oh measured oh measured ol measured output stops driing t ena t deca high-impedance state test conditions cause this oltage to be approximatel ol measured ol measured f i u re o u t ut e al e d is a le to outpu t pin f f i u re eui a le t d e i c e l o ad i o r a c m e as u r e e t s icl u d e s al l f i t u r es input or output f i ure o ltae r e er e c e l e e ls o r a c me asure et s e c et o u t ut e aled is a le c a a citi e lo adi o u t u t dela y s ad o lds a r e a s e d o st ada rd ca a ci t i e lo ad s f o al l i s s ee f i ur e f i ur e s o s o o u t u t d e la ys a d o lds a r y i t loa d ca a ci ta c e n o t e t a t t i s r a o r der a t i do es o t a ly to o u t u t dis a l e dela y s s e e t e o u t ut dis a l e t i e s e c t io t e r a s o f i ur e f i ur e a d f i ur e a y o t e liea r o u tside te ra es s o o r t y i c a l o u t ut d e la y s l o ad c a a c i t a ce ad t y i - cal o u t u t ris e f al l t i e m i s l o ad ca a c i t a c e load capacitance f nominal x output dela or hold s f i u re t y ic a l o u t ut d e l a y or h o ld s l oad ca a c i t a c e at ma case t e er atu r e load capacitance f fall time rise time x ris e and fall time s s to to x f i u re t y ic a l o u t ut r i s e f a ll ti e ddex t m a load capacitance f fall time rise time x ris e and fall time s s to to x f i u re t y ic a l o u t ut r i s e f a ll ti e ddex t m i rev. 0 | page 23 of 28
adsst-sharc-melody-ultra t ca s e = t am b + ( pd ? ca ) enviro nme n tal co nditio ns ther m al c h a r act e ris t ics w h er e: the s h arc m e lo d y u l t r a is p a cka g e d i n a 22 5-le ad mi ni b a l l gr id ar ra y (mb g a). the s h arc m e lo d y u l t r a is sp e c if ie d fo r a cas e t e m p er a t ur e (t ca se ). t o en s u r e tha t t h e t case sp e c if ica t ion is n o t exceeded , a h e a t sink and/o r a n a i r f lo w s o ur ce ma y b e us e d . u s e t h e ce n t er b l o c k o f g r o u n d p i n s (m b g a b a l l s: f6C10, g6C10, h6C10, j6C10, k6C10) to p r o v ide th er mal p a t h wa ys t o th e p r in t e d cir c ui t bo a r d s g r o u nd p l an e . a h e a t sink sh o u ld be a t t a ch e d t o t h e g r o u n d pl an e w i t h a t h er mal ad h e si v e as clos e as po s s i b l e t o th e th e r m a l pa th w a y s . t ca s e = c a s e t e m p er a t ur e ( m e a s u r e d o n t o p s u r f ace o f p a cka g e ) pd = p o w e r dissi p a t ion in w (t his va l u e dep e nds u p o n t h e sp e - c i f i c ap p l i c at i o n ; a m e t h o d f o r c a l c u l at i n g pd is s h o w n in t h e s e c t ion o n p a ge 22). p o w e r dissi p a t i o n ? ca = v a l u e f r o m , b e lo w . t a b l e 7 table 7. airflo w over package vs. ? ca airflow (linear ft/min) 0 200 400 ca (c/ w) 1 1 7 . 9 1 5 . 2 1 3 . 7 1 ? jc = 6.8c/w. rev. 0 page 24 of 28
adsst -sharc-melody-ultra pin conf iguration tale - l e ad metric mb ga pi assiets pbga pi nuer meoic pbga pi nuer meoic pbga pi n u e r m e o i c pbga pi nuer meoic pbga pi n u e r m e o i c a 0 1 n c d 0 1 t d o g 0 1 f l a g 1 k 0 1 time x p n 0 1 addr[14 ] a 0 2 b m s t r d 0 2 t c k g 0 2 f l a g 2 k 0 2 addr[22 ] n 0 2 addr[15 ] a03 bms d 0 3 f l a g 1 1 g 0 3 f l a g 4 k 0 3 addr[20 ] n 0 3 addr[10 ] a04 spids d 0 4 m i s o g 0 4 f l a g 3 k 0 4 addr[23 ] n 0 4 addr[5 ] a 0 5 e b o o t d 0 5 s c l k 0 g 0 5 v ddex t k 0 5 v ddin t n 0 5 addr[1 ] a 0 6 l b o o t d 0 6 d 1 b g 0 6 g n d k 0 6 g n d n 0 6 ms0 a 0 7 s c l k 2 d 0 7 f s 1 g 0 7 g n d k 0 7 g n d n 0 7 br5 a 0 8 d 3 b d 0 8 v ddin t g08 g n d k 0 8 g n d n 0 8 br2 a 0 9 l 0 d a t [ 4 ] d 0 9 s c l k 3 g 0 9 g n d k 0 9 g n d n 0 9 b r s t a 1 0 l 0 a c k d 1 0 l0dat[5 ] g 1 0 g n d k 1 0 g n d n 1 0 s d c k e a 1 1 l0dat[2 ] d 1 1 l0dat[3 ] g 1 1 v ddex t k 1 1 v ddin t n 1 1 cs a 1 2 l1dat[6 ] d 1 2 l1dat[5 ] g 1 2 data[34 ] k 1 2 data[22 ] n 1 2 c l k _ c f g 1 a 1 3 l 1 c l k d 1 3 data[42 ] g 1 3 data[35 ] k 1 3 data[19 ] n 1 3 c l k _ c f g 0 a 1 4 l1dat[2 ] d 1 4 data[46 ] g 1 4 data[33 ] k 1 4 data[21 ] n 1 4 av dd a 1 5 n c d 1 5 data[44 ] g 1 5 data[32 ] k 1 5 data[23 ] n 1 5 dmar1 b01 trst e 0 1 f l a g 1 0 h 0 1 f l a g 0 l 0 1 addr[19 ] p 0 1 addr[13 ] b 0 2 t d i e 0 2 reset h02 irq0 l 0 2 a d d r [ 1 7 ] p 0 2 addr[9 ] b 0 3 r p b a e 0 3 f l a g 8 h 0 3 v ddin t l 0 3 addr[21 ] p 0 3 addr[8 ] b 0 4 m o s i e 0 4 d 0 a h 0 4 irq1 l 0 4 a d d r [ 2 ] p 0 4 addr[4 ] b 0 5 f s 0 e 0 5 v ddex t h 0 5 v ddin t l 0 5 v ddex t p 0 5 ms2 b 0 6 s c l k 1 e 0 6 v ddin t h06 g n d l 0 6 v ddin t p 0 6 sbts b 0 7 d 2 b e 0 7 v ddex t h 0 7 g n d l 0 7 v ddex t p 0 7 br4 b 0 8 d 3 a e 0 8 v ddin t h08 g n d l 0 8 v ddin t p 0 8 br1 b 0 9 l 0 d a t [ 7 ] e 0 9 v ddex t h 0 9 g n d l 0 9 v ddex t p 0 9 s d c l k 1 b 1 0 l 0 c l k e 1 0 v ddin t h10 g n d l 1 0 v ddin t p 1 0 s d c l k 0 b 1 1 l 0 d a t [ 1 ] e 1 1 v ddex t h 1 1 v ddin t l 1 1 v ddex t p 1 1 r e d y b 1 2 l1dat[4 ] e 1 2 l0dat[0 ] h 1 2 data[29 ] l 1 2 cas p 1 2 c l k i n b 1 3 l 1 a c k e 1 3 data[39 ] h 1 3 data[28 ] l 1 3 data[20 ] p 1 3 d q m b 1 4 l1dat[0 ] e 1 4 data[43 ] h 1 4 data[30 ] l 1 4 data[16 ] p 1 4 a g n d b15 rstout 1 e 1 5 data[41 ] h 1 5 data[31 ] l 1 5 data[18 ] p 1 5 dmar2 c 0 1 t m s f 0 1 f l a g 5 j 0 1 irq2 m 0 1 a d d r [ 1 6 ] r 0 1 n c c02 emu f 0 2 f l a g 7 j 0 2 i d 1 m 0 2 addr[12 ] r 0 2 addr[11 ] c 0 3 g n d f 0 3 f l a g 9 j 0 3 i d 2 m 0 3 addr[18 ] r 0 3 addr[7 ] c 0 4 s p i c l k f 0 4 f l a g 6 j 0 4 i d 0 m 0 4 addr[6 ] r 0 4 addr[3 ] c 0 5 d 0 b f 0 5 v ddin t j05 v ddex t m 0 5 addr[0 ] r 0 5 ms3 c 0 6 d 1 a f 0 6 g n d j 0 6 g n d m 0 6 ms1 r06 pa c 0 7 d 2 a f 0 7 g n d j 0 7 g n d m 0 7 br6 r07 br3 c 0 8 f s 2 f 0 8 g n d j 0 8 g n d m 0 8 v ddex t r 0 8 rd c 0 9 f s 3 f 0 9 g n d j 0 9 g n d m 0 9 wr r 0 9 c l k o u t c 1 0 l0dat[6 ] f 1 0 g n d j 1 0 g n d m 1 0 s d a 1 0 r 1 0 hbr c 1 1 l 1 d a t [ 7 ] f 1 1 v ddin t j11 v ddex t m 1 1 ras r11 hbg c 1 2 l1dat[3 ] f 1 2 data[37 ] j 1 2 data[26 ] m 1 2 a c k r 1 2 clkdbl c 1 3 l1dat[1 ] f 1 3 data[40 ] j 1 3 data[24 ] m 1 3 data[17 ] r 1 3 x t a l c 1 4 data[45 ] f14 data[38 ] j 1 4 data[25 ] m 1 4 dmag1 r14 sdwe c 1 5 data[47 ] f15 data[36 ] j 1 5 data[27 ] m 1 5 dmag2 r 1 5 n c 1 rstout exi s t s on ly fo r si li c o n revi si on s 1.2 a n d gr ea t e r. l e a v e t h i s pi n un con n e ct ed for si li con revi si on s 0.3, 1.0, a n d 1.1. rev. 0 | page 25 of 28
adsst-sharc-melody-ultra pin laou t summar ddint ddext gnd agnd add signal use the center bloc of ground pins to proide thermal pathas to the printed circuit board ground plane e r p n m l h g f e d c b a f i g u re 21. 22 5-l e a d m e t r i c m b g a pin a s s i g n ment s, bot t o m vi ew , su m m ar y rev. 0 page 26 of 28
adsst -sharc-melody-ultra outline dimensions 0.70 0.60 0.50 1.70 ma x 1.00 bsc a b c d e f g h j k l m n r p 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 seating plane 1.10 max 0.20 max coplanarit detaila ball diameter 0.30 min 17.00 bsc 17.00 bsc top vie bottom vie pin 1 indicato r pin 1 corne r 14.00 bsc s notes 1. dimensions are in millimeters. 2. actal position of the ball grid is ithin 0.25 of its ideal position relative to the package edges. 3. actal position of each ball is ithin 0.10 of its ideal position relative to the ball grid. compliant to jedec standards mo-192-aaf 2 detail a f i g u re 22. 22 5-ba l l m i ni-b a ll g r id a r r a y [m bg a ] (ca-22 5) di me nsio ns sho w n i n mi ll im e t e r s esd caution esd (electrostatic discharge) sensitive device. ele c trosta tic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge with out detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity. orderi ng gide table 9. part number 1, 2 case tempera t u re range instruction rate on-chip sram operating voltage adsst-21161nkca100 0c to +85c 100 mh z 1 mbit 1.8 v int/3.3 v e x t adsst-21161ncca100 C40c to +105c 100 mh z 1 mbit 1.8 v int/3.3 v e x t 1 these parts are pa ckaged in a 225-le a d mini-ball grid arr a y (mbga). 2 th ese pro d uct s a r e s o l d a s pa rt o f a c h i p set , bun dle d wi t h n e ces s a ry a ppli c a t i o n soft wa re un de r speci a l pa rt n u m b ers. c o n t a ct a d i di r e ct ly for m o re inf o rmation. rev. 0 | page 27 of 28
adsst-sharc-melody-ultra rev. 0 | page 28 of 28 notes aalo de ices ic all rits resere d tra d e ars ad reistered tra d ear s are te roer ty o t eir resecti e c o a ies c

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